driver/ddr: Add 256 byte interleaving support

[kernel/u-boot.git] / README

diff --git a/README b/README
index 355e898..f51f17e 100644 (file)
--- a/README
+++ b/README
@@ -497,6 +497,11 @@ The following options need to be configured:
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
 
+               CONFIG_SYS_FSL_DDR_INTLV_256B
+               DDR controller interleaving on 256-byte. This is a special
+               interleaving mode, handled by Dickens for Freescale layerscape
+               SoCs with ARM core.
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO