Software Configuration:
=======================
-Configuration is usually done using C preprocessor defines; the
-rationale behind that is to avoid dead code whenever possible.
-
-There are two classes of configuration variables:
-
-* Configuration _OPTIONS_:
- These are selectable by the user and have names beginning with
- "CONFIG_".
-
-* Configuration _SETTINGS_:
- These depend on the hardware etc. and should not be meddled with if
- you don't know what you're doing; they have names beginning with
- "CONFIG_SYS_".
-
-Previously, all configuration was done by hand, which involved creating
-symbolic links and editing configuration files manually. More recently,
-U-Boot has added the Kbuild infrastructure used by the Linux kernel,
-allowing you to use the "make menuconfig" command to configure your
-build.
-
-
Selection of Processor Architecture and Board Type:
---------------------------------------------------
the "64" category of the Power ISA). This is necessary for ePAPR
compliance, among other possible reasons.
- CONFIG_SYS_FSL_TBCLK_DIV
-
- Defines the core time base clock divider ratio compared to the
- system clock. On most PQ3 devices this is 8, on newer QorIQ
- devices it can be 16 or 32. The ratio varies from SoC to Soc.
-
- CONFIG_SYS_FSL_PCIE_COMPAT
-
- Defines the string to utilize when trying to match PCIe device
- tree nodes for the given platform.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
- CONFIG_SYS_FSL_DSP_DDR_ADDR
- This value denotes start offset of DDR memory which is
- connected exclusively to the DSP cores.
-
- CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
- This value denotes start offset of M2 memory
- which is directly connected to the DSP core.
-
- CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
- This value denotes start offset of M3 memory which is directly
- connected to the DSP core.
-
- CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
- This value denotes start offset of DSP CCSR space.
-
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL SoC's.
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
- CONFIG_SYS_CPC_REINIT_F
- This CONFIG is defined when the CPC is configured as SRAM at the
- time of U-Boot entry and is required to be re-initialized.
-
- Generic CPU options:
- CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
-
- Defines the endianess of the CPU. Implementation of those
- values is arch specific.
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
- CONFIG_SYS_FSL_DDRC_GEN1
- Freescale DDR1 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN2
- Freescale DDR2 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN3
- Freescale DDR3 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN4
- Freescale DDR4 controller.
-
- CONFIG_SYS_FSL_DDRC_ARM_GEN3
- Freescale DDR3 controller for ARM-based SoCs.
-
- CONFIG_SYS_FSL_DDR1
- Board config to use DDR1. It can be enabled for SoCs with
- Freescale DDR1 or DDR2 controllers, depending on the board
- implemetation.
-
- CONFIG_SYS_FSL_DDR2
- Board config to use DDR2. It can be enabled for SoCs with
- Freescale DDR2 or DDR3 controllers, depending on the board
- implementation.
-
- CONFIG_SYS_FSL_DDR3
- Board config to use DDR3. It can be enabled for SoCs with
- Freescale DDR3 or DDR3L controllers.
-
- CONFIG_SYS_FSL_DDR3L
- Board config to use DDR3L. It can be enabled for SoCs with
- DDR3L controllers.
-
- CONFIG_SYS_FSL_IFC_BE
- Defines the IFC controller register space as Big Endian
-
- CONFIG_SYS_FSL_IFC_LE
- Defines the IFC controller register space as Little Endian
-
CONFIG_SYS_FSL_IFC_CLK_DIV
Defines divider of platform clock(clock input to IFC controller).
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_BE
- Defines the DDR controller register space as Big Endian
-
- CONFIG_SYS_FSL_DDR_LE
- Defines the DDR controller register space as Little Endian
-
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- CONFIG_SYS_FSL_DDR_INTLV_256B
- DDR controller interleaving on 256-byte. This is a special
- interleaving mode, handled by Dickens for Freescale layerscape
- SoCs with ARM core.
-
- CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
- Number of controllers used as main memory.
-
- CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
- Number of controllers used for other than main memory.
-
- CONFIG_SYS_FSL_SEC_BE
- Defines the SEC controller register space as Big Endian
-
- CONFIG_SYS_FSL_SEC_LE
- Defines the SEC controller register space as Little Endian
-
- MIPS CPU options:
CONFIG_XWAY_SWAP_BYTES
the defaults discussed just above.
- Cache Configuration for ARM:
- CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
- controller
CONFIG_SYS_PL310_BASE - Physical base address of PL310
controller register space
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_SMC91111
- Support for SMSC's LAN91C111 chip
-
- CONFIG_SMC91111_BASE
- Define this to hold the physical address
- of the device (I/O space)
-
- CONFIG_SMC_USE_32_BIT
- Define this if data bus is 32 bits
-
- CONFIG_SMC_USE_IOFUNCS
- Define this to use i/o functions instead of macros
- (some hardware wont work with macros)
-
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
Define this if you have more then 3 PHYs.
the appropriate value in Hz.
- MMC Support:
- The MMC controller on the Intel PXA is supported. To
- enable this define CONFIG_MMC. The MMC can be
- accessed from the boot prompt by mapping the device
- to physical memory similar to flash. Command line is
- enabled with CONFIG_CMD_MMC. The MMC driver also works with
- the FAT fs. This is enabled with CONFIG_CMD_FAT.
-
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller
- Keyboard Support:
See Kconfig help for available keyboard drivers.
-- LCD Support: CONFIG_LCD
-
- Define this to enable LCD support (for output to LCD
- display); also select one of the supported displays
- by defining one of these:
-
- CONFIG_NEC_NL6448AC33:
-
- NEC NL6448AC33-18. Active, color, single scan.
-
- CONFIG_NEC_NL6448BC20
-
- NEC NL6448BC20-08. 6.5", 640x480.
- Active, color, single scan.
-
- CONFIG_NEC_NL6448BC33_54
-
- NEC NL6448BC33-54. 10.4", 640x480.
- Active, color, single scan.
-
- CONFIG_SHARP_16x9
-
- Sharp 320x240. Active, color, single scan.
- It isn't 16x9, and I am not sure what it is.
-
- CONFIG_SHARP_LQ64D341
-
- Sharp LQ64D341 display, 640x480.
- Active, color, single scan.
-
- CONFIG_HLD1045
-
- HLD1045 display, 640x480.
- Active, color, single scan.
-
- CONFIG_OPTREX_BW
-
- Optrex CBL50840-2 NF-FW 99 22 M5
- or
- Hitachi LMG6912RPFC-00T
- or
- Hitachi SP14Q002
-
- 320x240. Black & white.
-
- CONFIG_LCD_ALIGNMENT
-
- Normally the LCD is page-aligned (typically 4KB). If this is
- defined then the LCD will be aligned to this value instead.
- For ARM it is sometimes useful to use MMU_SECTION_SIZE
- here, since it is cheaper to change data cache settings on
- a per-section basis.
-
-
- CONFIG_LCD_ROTATION
-
- Sometimes, for example if the display is mounted in portrait
- mode or even if it's mounted landscape but rotated by 180degree,
- we need to rotate our content of the display relative to the
- framebuffer, so that user can read the messages which are
- printed out.
- Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
- initialized with a given rotation from "vl_rot" out of
- "vidinfo_t" which is provided by the board specific code.
- The value for vl_rot is coded as following (matching to
- fbcon=rotate:<n> linux-kernel commandline):
- 0 = no rotation respectively 0 degree
- 1 = 90 degree rotation
- 2 = 180 degree rotation
- 3 = 270 degree rotation
-
- If CONFIG_LCD_ROTATION is not defined, the console will be
- initialized with 0degree rotation.
-
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
- CONFIG_SYS_FPGA_PROG_FEEDBACK
-
- Enable printing of hash marks during FPGA configuration.
-
CONFIG_SYS_FPGA_CHECK_BUSY
Enable checks on FPGA configuration interface busy
If defined, a function that provides delays in the FPGA
configuration driver.
- CONFIG_SYS_FPGA_CHECK_CTRLC
- Allow Control-C to interrupt FPGA configuration
-
CONFIG_SYS_FPGA_CHECK_ERROR
Check for configuration errors during FPGA bitfile
overwriting the architecture dependent default
settings.
-- Frame Buffer Address:
- CONFIG_FB_ADDR
-
- Define CONFIG_FB_ADDR if you want to use specific
- address for frame buffer. This is typically the case
- when using a graphics controller has separate video
- memory. U-Boot will then place the frame buffer at
- the given address instead of dynamically reserving it
- in system RAM by calling lcd_setmem(), which grabs
- the memory for the frame buffer depending on the
- configured panel size.
-
- Please see board_init_f function.
-
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
Non-cached memory is only supported on 32-bit ARM at present.
-- CONFIG_SYS_BOOTM_LEN:
- Normally compressed uImages are limited to an
- uncompressed size of 8 MBytes. If this is not enough,
- you can define CONFIG_SYS_BOOTM_LEN in your board config file
- to adjust this setting to your needs.
-
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
-- CONFIG_SYS_BOOT_RAMDISK_HIGH:
- Enable initrd_high functionality. If defined then the
- initrd_high feature is enabled and the bootm ramdisk subcommand
- is enabled.
-
- CONFIG_SYS_BOOT_GET_CMDLINE:
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
-- CONFIG_SYS_MAX_FLASH_SECT:
- Max number of sectors on a Flash chip
-
-- CONFIG_SYS_FLASH_ERASE_TOUT:
- Timeout for Flash erase operations (in ms)
-
-- CONFIG_SYS_FLASH_WRITE_TOUT:
- Timeout for Flash write operations (in ms)
-
-- CONFIG_SYS_FLASH_LOCK_TOUT
- Timeout for Flash set sector lock bit operation (in ms)
-
-- CONFIG_SYS_FLASH_UNLOCK_TOUT
- Timeout for Flash clear lock bits operation (in ms)
-
- CONFIG_SYS_FLASH_PROTECTION
If defined, hardware flash sectors protection is used
instead of U-Boot software protection.
-- CONFIG_SYS_DIRECT_FLASH_TFTP:
-
- Enable TFTP transfers directly to flash memory;
- without this option such a download has to be
- performed in two steps: (1) download to RAM, and (2)
- copy from RAM to flash.
-
- The two-step approach is usually more reliable, since
- you can check if the download worked before you erase
- the flash, but in some situations (when system RAM is
- too limited to allow for a temporary copy of the
- downloaded image) this option may be very useful.
-
- CONFIG_SYS_FLASH_CFI:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
s29ws-n MirrorBit flash has non-standard addresses for buffered
write commands.
-- CONFIG_SYS_FLASH_QUIET_TEST
- If this option is defined, the common CFI flash doesn't
- print it's warning upon not recognized FLASH banks. This
- is useful, if some of the configured banks are only
- optionally available.
-
- CONFIG_FLASH_SHOW_PROGRESS
If defined (must be an integer), print out countdown
digits and dots. Recommended value: 45 (9..1) for 80
one, specify here. Note that the value must resolve
to something your driver can deal with.
-- CONFIG_SYS_DDR_RAW_TIMING
- Get DDR timing information from other than SPD. Common with
- soldered DDR chips onboard without SPD. DDR raw timing
- parameters are extracted from datasheet and hard-coded into
- header files or board specific files.
-
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.
- CONFIG_FSL_DDR_BIST
Enable built-in memory test for Freescale DDR controllers.
-- CONFIG_SYS_83XX_DDR_USES_CS0
- Only for 83xx systems. If specified, then DDR should
- be configured using CS0 and CS1 instead of CS2 and CS3.
-
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't