SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
- CONFIG_SPL_STACK_R_ADDR points into SDRAM
- - preloader_console_init() can be called here - typically this is
- done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
- spl_board_init() function containing this call
- - loads U-Boot or (in falcon mode) Linux
-
-
-Configuration Options:
-----------------------
-
-Configuration depends on the combination of board and CPU type; all
-such information is kept in a configuration file
-"include/configs/<board_name>.h".
-
-Example: For a TQM823L module, all configuration settings are in
-"include/configs/TQM823L.h".
-
-
-Many of the options are named exactly as the corresponding Linux
-kernel configuration options. The intention is to make it easier to
-build a config tool - later.
-
-- ARM Platform Bus Type(CCI):
- CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
- provides full cache coherency between two clusters of multi-core
- CPUs and I/O coherency for devices and I/O masters
-
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
Defines the SEC controller register space as Little Endian
- MIPS CPU options:
- CONFIG_SYS_INIT_SP_OFFSET
-
- Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
- pointer. This is needed for the temporary stack before
- relocation.
-
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
- CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
- txfilltuning field in the EHCI controller on reset.
-
CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
HW module registers.
CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_MAX_FOOTPRINT
- Maximum size in memory allocated to the SPL, BSS included.
- When defined, the linker checks that the actual memory
- used by SPL from _start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_MAX_SIZE
- Maximum size of the SPL image (text, data, rodata, and
- linker lists sections), BSS excluded.
- When defined, the linker checks that the actual size does
- not exceed it.
-
- CONFIG_SPL_RELOC_TEXT_BASE
- Address to relocate to. If unspecified, this is equal to
- CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
-
- CONFIG_SPL_BSS_START_ADDR
- Link address for the BSS within the SPL binary.
-
- CONFIG_SPL_BSS_MAX_SIZE
- Maximum size in memory allocated to the SPL BSS.
- When defined, the linker checks that the actual memory used
- by SPL from __bss_start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_STACK
- Adress of the start of the stack SPL will use
-
CONFIG_SPL_PANIC_ON_RAW_IMAGE
When defined, SPL will panic() if the image it has
loaded does not have a signature.
consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
- CONFIG_SPL_RELOC_STACK
- Adress of the start of the stack SPL will use after
- relocation. If unspecified, this is equal to
- CONFIG_SPL_STACK.
-
- CONFIG_SYS_SPL_MALLOC_START
- Starting address of the malloc pool used in SPL.
- When this option is set the full malloc is used in SPL and
- it is set up by spl_init() and before that, the simple malloc()
- can be used if CONFIG_SYS_MALLOC_F is defined.
-
- CONFIG_SYS_SPL_MALLOC_SIZE
- The size of the malloc pool used in SPL.
-
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
- CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
- CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
- Sector and number of sectors to load kernel argument
- parameters from when MMC is being used in raw mode
- (for falcon mode)
-
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- Filename to read to load U-Boot when reading from filesystem
-
- CONFIG_SPL_FS_LOAD_KERNEL_NAME
- Filename to read to load kernel uImage when reading
- from filesystem (for Falcon mode)
-
- CONFIG_SPL_FS_LOAD_ARGS_NAME
- Filename to read to load kernel argument parameters
- when reading from filesystem (for Falcon mode)
-
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
start.S waits for the rest of the SPL to load before
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SPL_COMMON_INIT_DDR
- Set for common ddr init with serial presence detect in
- SPL binary.
-
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SPL_PAD_TO
- Image offset to which the SPL should be padded before appending
- the SPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
- CONFIG_SPL_TARGET
- Final target image containing SPL and payload. Some SPLs
- use an arch-specific makefile fragment instead, for
- example if more than one image needs to be produced.
-
CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
-- TPL framework
- CONFIG_TPL
- Enable building of TPL globally.
-
- CONFIG_TPL_PAD_TO
- Image offset to which the TPL should be padded before appending
- the TPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
- CONFIG_SYS_MALLOC_SIMPLE
Provides a simple and small malloc() and calloc() for those
boards which do not use the full malloc in SPL (which is
- enabled with CONFIG_SYS_SPL_MALLOC_START).
+ enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_NONCACHED_MEMORY:
Size of non-cached memory area. This area of memory will be
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
- If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
- forced to a value that ensures that CCSR is not relocated.
-
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
-- CONFIG_SYS_GBL_DATA_OFFSET:
-
- Offset of the initial data structure in the memory
- area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
- CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
- data is located at the end of the available space
- (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- GENERATED_GBL_DATA_SIZE), and the initial stack is just
- below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
- CONFIG_SYS_GBL_DATA_OFFSET) downward.
-
- Note:
- On the MPC824X (or other systems that use the data
- cache for initial memory) the address chosen for
- CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
- point to an otherwise UNUSED address space between
- the top of RAM and the start of the PCI space.
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd'
loads - load S-Record file over serial line
loadb - load binary file over serial line (kermit mode)
+loadm - load binary blob from source address to destination address
md - memory display
mm - memory modify (auto-incrementing)
nm - memory modify (constant address)