rockchip: rk3128-cru: sync the clock dt-binding header from Linux

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index 351c039..d75c3fb 100644 (file)
--- a/README
+++ b/README
@@ -298,7 +298,7 @@ The following options need to be configured:
 
                Enables a workaround for erratum A004510.  If set,
                then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
-               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+               CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
 
                CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
                CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@@ -314,7 +314,7 @@ The following options need to be configured:
                See Freescale App Note 4493 for more information about
                this erratum.
 
-               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+               CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
@@ -330,7 +330,7 @@ The following options need to be configured:
                Freescale DDR driver in use. This type of DDR controller is
                found in mpc83xx, mpc85xx as well as some ARM core SoCs.
 
-               CONFIG_SYS_FSL_DDR_ADDR
+               CFG_SYS_FSL_DDR_ADDR
                Freescale DDR memory-mapped register base.
 
                CONFIG_SYS_FSL_IFC_CLK_DIV
@@ -339,7 +339,7 @@ The following options need to be configured:
                CONFIG_SYS_FSL_LBC_CLK_DIV
                Defines divider of platform clock(clock input to eLBC controller).
 
-               CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+               CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
                Physical address from the view of DDR controllers. It is the
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
@@ -1473,25 +1473,6 @@ Configuration Settings:
                boards which do not use the full malloc in SPL (which is
                enabled with CONFIG_SYS_SPL_MALLOC).
 
-- CONFIG_SYS_NONCACHED_MEMORY:
-               Size of non-cached memory area. This area of memory will be
-               typically located right below the malloc() area and mapped
-               uncached in the MMU. This is useful for drivers that would
-               otherwise require a lot of explicit cache maintenance. For
-               some drivers it's also impossible to properly maintain the
-               cache. For example if the regions that need to be flushed
-               are not a multiple of the cache-line size, *and* padding
-               cannot be allocated between the regions to align them (i.e.
-               if the HW requires a contiguous array of regions, and the
-               size of each region is not cache-aligned), then a flush of
-               one region may result in overwriting data that hardware has
-               written to another region in the same cache-line. This can
-               happen for example in network drivers where descriptors for
-               buffers are typically smaller than the CPU cache-line (e.g.
-               16 bytes vs. 32 or 64 bytes).
-
-               Non-cached memory is only supported on 32-bit ARM at present.
-
 - CONFIG_SYS_BOOTMAPSZ:
                Maximum size of memory mapped by the startup code of
                the Linux kernel; all data that must be processed by