FAT32: fix broken root directory handling.

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index 68f1720..c9fb284 100644 (file)
--- a/README
+++ b/README
@@ -143,9 +143,9 @@ Directory Hierarchy:
     /cpu               CPU specific files
       /arm720t         Files specific to ARM 720 CPUs
       /arm920t         Files specific to ARM 920 CPUs
-        /at91rm9200    Files specific to Atmel AT91RM9200 CPU
-        /imx           Files specific to Freescale MC9328 i.MX CPUs
-        /s3c24x0       Files specific to Samsung S3C24X0 CPUs
+       /at91rm9200     Files specific to Atmel AT91RM9200 CPU
+       /imx            Files specific to Freescale MC9328 i.MX CPUs
+       /s3c24x0        Files specific to Samsung S3C24X0 CPUs
       /arm925t         Files specific to ARM 925 CPUs
       /arm926ejs       Files specific to ARM 926 CPUs
       /arm1136         Files specific to ARM 1136 CPUs
@@ -1495,6 +1495,16 @@ The following options need to be configured:
 
                #define I2C_DELAY  udelay(2)
 
+               CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
+
+               If your arch supports the generic GPIO framework (asm/gpio.h),
+               then you may alternatively define the two GPIOs that are to be
+               used as SCL / SDA.  Any of the previous I2C_xxx macros will
+               have GPIO-based defaults assigned to them as appropriate.
+
+               You should define these to the GPIO value as given directly to
+               the generic GPIO functions.
+
                CONFIG_SYS_I2C_INIT_BOARD
 
                When a board is reset during an i2c bus transfer
@@ -2504,7 +2514,7 @@ to save the current settings.
          I2C muxes, you can define here, how to reach this
          EEPROM. For example:
 
-         #define CONFIG_I2C_ENV_EEPROM_BUS       "pca9547:70:d\0"
+         #define CONFIG_I2C_ENV_EEPROM_BUS       "pca9547:70:d\0"
 
          EEPROM which holds the environment, is reached over
          a pca9547 i2c mux with address 0x70, channel 3.