Prepare v2014.01

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index e58e9c0..aea82be 100644 (file)
--- a/README
+++ b/README
@@ -423,6 +423,11 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 
+               CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               Single Source Clock is clocking mode present in some of FSL SoC's.
+               In this mode, a single differential clock is used to supply
+               clocks to the sysclock, ddrclock and usbclock.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -2751,6 +2756,12 @@ CBFS (Coreboot Filesystem) support
                Define this option to use the Bank addr/Extended addr
                support on SPI flashes which has size > 16Mbytes.
 
+               CONFIG_SF_DUAL_FLASH            Dual flash memories
+
+               Define this option to use dual flash support where two flash
+               memories can be connected with a given cs line.
+               currently Xilinx Zynq qspi support these type of connections.
+
 - SystemACE Support:
                CONFIG_SYSTEMACE