Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
See Freescale App Note 4493 for more information about
this erratum.
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
- CONFIG_SYS_FSL_DDR_ADDR
+ CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
- same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
+ same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- MIPS CPU options:
be swapped if a flash programmer is used.
- ARM options:
- CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+ CFG_SYS_EXCEPTION_VECTORS_HIGH
Select high exception vectors of the ARM core, e.g., do not
clear the V bit of the c1 register of CP15.
such as ARM architectural timer initialization.
- Linux Kernel Interface:
- CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
-
- When transferring memsize parameter to Linux, some versions
- expect it to be in bytes, others in MB.
- Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
-
CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be
the defaults discussed just above.
- Cache Configuration for ARM:
- CONFIG_SYS_PL310_BASE - Physical base address of PL310
+ CFG_SYS_PL310_BASE - Physical base address of PL310
controller register space
- Serial Ports:
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Serial Download Echo Mode:
- CONFIG_LOADS_ECHO
- If defined to 1, all characters received during a
- serial download (using the "loads" command) are
- echoed back. This might be needed by some terminal
- emulations (like "cu"), but may as well just take
- time on others. This setting #define's the initial
- value of the "loads_echo" environment variable.
-
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
to 0 disables calling WATCHDOG_RESET() from the timer
interrupt.
-- Real-Time Clock:
-
- When CONFIG_CMD_DATE is selected, the type of the RTC
- has to be selected, too. Define exactly one of the
- following options:
-
- CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
- CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
- CONFIG_RTC_MC146818 - use MC146818 RTC
- CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
- CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
- CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
- CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC
- CONFIG_RTC_DS164x - use Dallas DS164x RTC
- CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
- CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
- CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
- CONFIG_SYS_RV3029_TCR - enable trickle charger on
- RV3029 RTC.
-
- Note that if the RTC uses I2C, then the I2C interface
- must also be configured. See I2C Support, below.
-
- GPIO Support:
- CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
-
- The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+ The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
chip-ngpio pairs that tell the PCA953X driver the number of
pins supported by a particular chip.
Support for generic parallel port TPM devices. Only one device
per system is supported at this time.
- CONFIG_TPM_TIS_BASE_ADDRESS
- Base address where the generic TPM device is mapped
- to. Contemporary x86 systems usually map it at
- 0xfed40000.
-
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
variable usbtty to be cdc_acm should suffice. The following
might be defined in YourBoardName.h
- CONFIG_USB_DEVICE
- Define this to build a UDC device
-
- CONFIG_USB_TTY
- Define this to have a tty type of device available to
- talk to the UDC device
-
CONFIG_USBD_HS
Define this to enable the high speed support for usb
device and usbtty. If this feature is enabled, a routine
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
-- Journaling Flash filesystem support:
- CONFIG_SYS_JFFS2_FIRST_SECTOR,
- CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
- Define these for a default partition on a NOR device
-
- Keyboard Support:
See Kconfig help for available keyboard drivers.
-- LCD Support: CONFIG_LCD
-
- Define this to enable LCD support (for output to LCD
- display); also select one of the supported displays
- by defining one of these:
-
- CONFIG_NEC_NL6448AC33:
-
- NEC NL6448AC33-18. Active, color, single scan.
-
- CONFIG_NEC_NL6448BC20
-
- NEC NL6448BC20-08. 6.5", 640x480.
- Active, color, single scan.
-
- CONFIG_NEC_NL6448BC33_54
-
- NEC NL6448BC33-54. 10.4", 640x480.
- Active, color, single scan.
-
- CONFIG_SHARP_16x9
-
- Sharp 320x240. Active, color, single scan.
- It isn't 16x9, and I am not sure what it is.
-
- CONFIG_SHARP_LQ64D341
-
- Sharp LQ64D341 display, 640x480.
- Active, color, single scan.
-
- CONFIG_HLD1045
-
- HLD1045 display, 640x480.
- Active, color, single scan.
-
- CONFIG_OPTREX_BW
-
- Optrex CBL50840-2 NF-FW 99 22 M5
- or
- Hitachi LMG6912RPFC-00T
- or
- Hitachi SP14Q002
-
- 320x240. Black & white.
-
- CONFIG_LCD_ALIGNMENT
-
- Normally the LCD is page-aligned (typically 4KB). If this is
- defined then the LCD will be aligned to this value instead.
- For ARM it is sometimes useful to use MMU_SECTION_SIZE
- here, since it is cheaper to change data cache settings on
- a per-section basis.
-
-
- CONFIG_LCD_ROTATION
-
- Sometimes, for example if the display is mounted in portrait
- mode or even if it's mounted landscape but rotated by 180degree,
- we need to rotate our content of the display relative to the
- framebuffer, so that user can read the messages which are
- printed out.
- Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
- initialized with a given rotation from "vl_rot" out of
- "vidinfo_t" which is provided by the board specific code.
- The value for vl_rot is coded as following (matching to
- fbcon=rotate:<n> linux-kernel commandline):
- 0 = no rotation respectively 0 degree
- 1 = 90 degree rotation
- 2 = 180 degree rotation
- 3 = 270 degree rotation
-
- If CONFIG_LCD_ROTATION is not defined, the console will be
- initialized with 0degree rotation.
-
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
Some PHY like Intel LXT971A need extra delay after
command issued before MII status register can be read
-- IP address:
- CONFIG_IPADDR
-
- Define a default value for the IP address to use for
- the default Ethernet interface, in case this is not
- determined through e.g. bootp.
- (Environment variable "ipaddr")
-
-- Server IP address:
- CONFIG_SERVERIP
-
- Defines a default value for the IP address of a TFTP
- server to contact when using the "tftboot" command.
- (Environment variable "serverip")
-
-- Gateway IP address:
- CONFIG_GATEWAYIP
-
- Defines a default value for the IP address of the
- default router where packets to other networks are
- sent to.
- (Environment variable "gatewayip")
-
-- Subnet mask:
- CONFIG_NETMASK
-
- Defines a default value for the subnet mask (or
- routing prefix) which is used to determine if an IP
- address belongs to the local subnet or needs to be
- forwarded through a router.
- (Environment variable "netmask")
-
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
with a list of GPIO LEDs that have inverted polarity.
- I2C Support:
- CONFIG_SYS_NUM_I2C_BUSES
+ CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware.
- if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+ if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
omit this define.
- CONFIG_SYS_I2C_MAX_HOPS
+ CFG_SYS_I2C_MAX_HOPS
define how many muxes are maximal consecutively connected
on one i2c bus. If you not use i2c muxes, omit this
define.
- CONFIG_SYS_I2C_BUSES
+ CFG_SYS_I2C_BUSES
hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
- a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
- CONFIG_SYS_NUM_I2C_BUSES = 9:
+ a board with CFG_SYS_I2C_MAX_HOPS = 1 and
+ CFG_SYS_NUM_I2C_BUSES = 9:
- CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
+ CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
You should define these to the GPIO value as given directly to
the generic GPIO functions.
- CONFIG_SYS_I2C_INIT_BOARD
-
- When a board is reset during an i2c bus transfer
- chips might think that the current transfer is still
- in progress. On some boards it is possible to access
- the i2c SCLK line directly, either by using the
- processor pin as a GPIO or by having a second pin
- connected to the bus. If this option is defined a
- custom i2c_init_board() routine in boards/xxx/board.c
- is run early in the boot sequence.
-
CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which
active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
- CONFIG_SYS_I2C_NOPROBES
+ CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
- when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
- is set, specify a list of bus-device pairs. Otherwise, specify
- a 1D array of device addresses
+ when the 'i2c probe' command is issued.
e.g.
- #undef CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+ #define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
- #define CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
-
- will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
-
- CONFIG_SYS_RTC_BUS_NUM
+ CFG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
configuration if the INIT_B line goes low (which
indicated a CRC error).
- CONFIG_SYS_FPGA_WAIT_INIT
+ CFG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to de-assert
after PROB_B has been de-asserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
- CONFIG_SYS_FPGA_WAIT_BUSY
+ CFG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to de-assert during
Virtex II FPGA configuration. The default is 5 ms.
- CONFIG_SYS_FPGA_WAIT_CONFIG
+ CFG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 ms.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
- CONFIG_SYS_NAND_ECCBYTES
+ CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+ CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SYS_NAND_U_BOOT_DST
+ CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
- CONFIG_SYS_NAND_U_BOOT_SIZE
+ CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load
- CONFIG_SYS_NAND_U_BOOT_START
+ CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
- Define this if you need to first read the OOB and then the
- data. This is used, for example, on davinci platforms.
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
-- CONFIG_SYS_BAUDRATE_TABLE:
+- CFG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
-- CONFIG_SYS_MEM_RESERVE_SECURE
+- CFG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
- If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+ If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable
gd->arch.secure_ram is used to track the location. In systems
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_LOADS_BAUD_CHANGE:
- Enable temporary baudrate change while serial download
-
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
-- CONFIG_SYS_FLASH_BASE:
+- CFG_SYS_FLASH_BASE:
Physical start address of Flash memory.
-- CONFIG_SYS_MONITOR_LEN:
- Size of memory reserved for monitor code, used to
- determine _at_compile_time_ (!) if the environment is
- embedded within the U-Boot image, or in a separate
- flash sector.
-
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_NONCACHED_MEMORY:
- Size of non-cached memory area. This area of memory will be
- typically located right below the malloc() area and mapped
- uncached in the MMU. This is useful for drivers that would
- otherwise require a lot of explicit cache maintenance. For
- some drivers it's also impossible to properly maintain the
- cache. For example if the regions that need to be flushed
- are not a multiple of the cache-line size, *and* padding
- cannot be allocated between the regions to align them (i.e.
- if the HW requires a contiguous array of regions, and the
- size of each region is not cache-aligned), then a flush of
- one region may result in overwriting data that hardware has
- written to another region in the same cache-line. This can
- happen for example in network drivers where descriptors for
- buffers are typically smaller than the CPU cache-line (e.g.
- 16 bytes vs. 32 or 64 bytes).
-
- Non-cached memory is only supported on 32-bit ARM at present.
-
-- CONFIG_SYS_BOOTMAPSZ:
+- CFG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
environment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
- and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
+ and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of
- CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
+ CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE:
- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
-- CONFIG_FLASH_SPANSION_S29WS_N
- s29ws-n MirrorBit flash has non-standard addresses for buffered
- write commands.
-
-- CONFIG_FLASH_SHOW_PROGRESS
- If defined (must be an integer), print out countdown
- digits and dots. Recommended value: 45 (9..1) for 80
- column displays, 15 (3..1) for 40 column displays.
-
-- CONFIG_FLASH_VERIFY
- If defined, the content of the flash (destination) is compared
- against the source after the write operation. An error message
- will be printed when the contents are not identical.
- Please note that this option is useless in nearly all cases,
- since such flash programming errors usually are detected earlier
- while unprotecting/erasing/programming. Please only enable
- this option if you really know what you are doing.
-
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
of environment data (variable area); in general, we support the
following configurations:
-- CONFIG_BUILD_ENVCRC:
-
- Builds up envcrc with the target environment so that external utils
- may easily extract it and embed it in final U-Boot images.
-
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
-- CONFIG_NS16550_MIN_FUNCTIONS:
- Define this if you desire to only have use of the NS16550_init
- and NS16550_putc functions for the serial driver located at
- drivers/serial/ns16550.c. This option is useful for saving
- space for already greatly restricted images, including but not
- limited to NAND_SPL configurations.
-
- CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs.
-- CONFIG_SYS_CCSRBAR:
+- CFG_SYS_CCSRBAR:
Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
-- CONFIG_SYS_CCSRBAR_PHYS:
+- CFG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
be set to that address. Otherwise, it should be set to the
is typically relocated on 36-bit builds. It is recommended
that this macro be defined via the _HIGH and _LOW macros:
- #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
- * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
+ #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+ * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
- Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
+- CFG_SYS_CCSRBAR_PHYS_HIGH:
+ Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically
either 0 (32-bit build) or 0xF (36-bit build). This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
- Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
+- CFG_SYS_CCSRBAR_PHYS_LOW:
+ Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
-- CONFIG_SYS_INIT_RAM_ADDR:
+- CFG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for
initial data and stack; please note that this must be
- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
-- CONFIG_SYS_MAMR_PTA:
- periodic timer for refresh
-
-- CONFIG_SYS_SRIO:
- Chip has SRIO or not
-
-- CONFIG_SRIO1:
- Board has SRIO 1 port available
-
-- CONFIG_SRIO2:
- Board has SRIO 2 port available
-
-- CONFIG_SRIO_PCIE_BOOT_MASTER
- Board can support master function for Boot from SRIO and PCIE
-
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region
Sets the EBC0_CFG register for the NDFC. If not defined
a default value will be used.
-- CONFIG_SPD_EEPROM
- Get DDR timing information from an I2C EEPROM. Common
- with pluggable memory modules such as SODIMMs
-
- SPD_EEPROM_ADDRESS
- I2C address of the SPD EEPROM
-
- CONFIG_SYS_SPD_BUS_NUM
If SPD EEPROM is on an I2C bus other than the first
one, specify here. Note that the value must resolve
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
-- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
- Option to disable subpage write in NAND driver
- driver that uses this:
- drivers/mtd/nand/raw/davinci_nand.c
-
Freescale QE/FMAN Firmware Support:
-----------------------------------
cause you grief during the initial boot! It is frequently not
used.
- CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+ CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger
projects / platform / kernel / u-boot.git / blobdiff