powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index 6852080..983d55e 100644 (file)
--- a/README
+++ b/README
@@ -413,11 +413,22 @@ The following options need to be configured:
                See Freescale App Note 4493 for more information about
                this erratum.
 
+               CONFIG_A003399_NOR_WORKAROUND
+               Enables a workaround for IFC erratum A003399. It is only
+               requred during NOR boot.
+
                CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
 
+               CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+               This value denotes start offset of M2 memory
+               which is directly connected to the DSP core.
+
+               CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+               This value denotes start offset of DSP CCSR space.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -1261,6 +1272,9 @@ The following options need to be configured:
                CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
                txfilltuning field in the EHCI controller on reset.
 
+               CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
+               interval for usb hub power-on delay.(minimum 100msec)
+
 - USB Device:
                Define the below if you wish to use the USB console.
                Once firmware is rebuilt from a serial console issue the
@@ -3961,6 +3975,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
                Board has SRIO 2 port available
 
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+               Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
                Virtual Address of SRIO port 'n' memory region