dm: core: Swap parameters of ofnode_write_prop()

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index 70c99aa..6b6f722 100644 (file)
--- a/README
+++ b/README
@@ -396,12 +396,6 @@ The following options need to be configured:
                Board config to use DDR3L. It can be enabled for SoCs with
                DDR3L controllers.
 
-               CONFIG_SYS_FSL_IFC_BE
-               Defines the IFC controller register space as Big Endian
-
-               CONFIG_SYS_FSL_IFC_LE
-               Defines the IFC controller register space as Little Endian
-
                CONFIG_SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to IFC controller).
 
@@ -419,11 +413,6 @@ The following options need to be configured:
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
 
-               CONFIG_SYS_FSL_DDR_INTLV_256B
-               DDR controller interleaving on 256-byte. This is a special
-               interleaving mode, handled by Dickens for Freescale layerscape
-               SoCs with ARM core.
-
                CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
                Number of controllers used as main memory.