arm/ls1021a: add PCIe settings

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index a28ff13..6800b95 100644 (file)
--- a/README
+++ b/README
@@ -1257,6 +1257,9 @@ The following options need to be configured:
                SoC, then define this variable and provide board
                specific code for the "hw_watchdog_reset" function.
 
+               CONFIG_AT91_HW_WDT_TIMEOUT
+               specify the timeout in seconds. default 2 seconds.
+
 - U-Boot Version:
                CONFIG_VERSION_VARIABLE
                If this variable is defined, an environment variable
@@ -4913,6 +4916,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_FSL_DDR_INTERACTIVE
                Enable interactive DDR debugging. See doc/README.fsl-ddr.
 
+- CONFIG_FSL_DDR_SYNC_REFRESH
+               Enable sync of refresh for multiple controllers.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.