Convert CONFIG_SYS_FSL_PCIE_COMPAT to Kconfig

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index ebfdced..4ef9e8c 100644 (file)
--- a/README
+++ b/README
@@ -300,11 +300,6 @@ The following options need to be configured:
                system clock.  On most PQ3 devices this is 8, on newer QorIQ
                devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 
-               CONFIG_SYS_FSL_PCIE_COMPAT
-
-               Defines the string to utilize when trying to match PCIe device
-               tree nodes for the given platform.
-
                CONFIG_SYS_FSL_ERRATUM_A004510
 
                Enables a workaround for erratum A004510.  If set,
@@ -330,31 +325,12 @@ The following options need to be configured:
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
 
-               CONFIG_SYS_FSL_DSP_DDR_ADDR
-               This value denotes start offset of DDR memory which is
-               connected exclusively to the DSP cores.
-
-               CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
-               This value denotes start offset of M2 memory
-               which is directly connected to the DSP core.
-
-               CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
-               This value denotes start offset of M3 memory which is directly
-               connected to the DSP core.
-
-               CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-               This value denotes start offset of DSP CCSR space.
-
                CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
                Single Source Clock is clocking mode present in some of FSL SoC's.
                In this mode, a single differential clock is used to supply
                clocks to the sysclock, ddrclock and usbclock.
 
 - Generic CPU options:
-               CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
-
-               Defines the endianess of the CPU. Implementation of those
-               values is arch specific.
 
                CONFIG_SYS_FSL_DDR
                Freescale DDR driver in use. This type of DDR controller is