/m68k Files generic to m68k architecture
/microblaze Files generic to microblaze architecture
/mips Files generic to MIPS architecture
- /nds32 Files generic to NDS32 architecture
/nios2 Files generic to Altera NIOS2 architecture
/powerpc Files generic to PowerPC architecture
/riscv Files generic to RISC-V architecture
SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
- CONFIG_SPL_STACK_R_ADDR points into SDRAM
- - preloader_console_init() can be called here - typically this is
- done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
- spl_board_init() function containing this call
- - loads U-Boot or (in falcon mode) Linux
-
-
-Configuration Options:
-----------------------
-
-Configuration depends on the combination of board and CPU type; all
-such information is kept in a configuration file
-"include/configs/<board_name>.h".
-
-Example: For a TQM823L module, all configuration settings are in
-"include/configs/TQM823L.h".
-
-
-Many of the options are named exactly as the corresponding Linux
-kernel configuration options. The intention is to make it easier to
-build a config tool - later.
-
-- ARM Platform Bus Type(CCI):
- CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
- provides full cache coherency between two clusters of multi-core
- CPUs and I/O coherency for devices and I/O masters
-
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-Boot entry and is required to be re-initialized.
- CONFIG_DEEP_SLEEP
- Indicates this SoC supports deep sleep feature. If deep sleep is
- supported, core will start to execute uboot when wakes up.
-
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
- CONFIG_SYS_FSL_HAS_DP_DDR
- Defines the SoC has DP-DDR used for DPAA.
-
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
Defines the SEC controller register space as Little Endian
- MIPS CPU options:
- CONFIG_SYS_INIT_SP_OFFSET
-
- Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
- pointer. This is needed for the temporary stack before
- relocation.
-
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
- Keyboard Support:
See Kconfig help for available keyboard drivers.
-- Video support:
- CONFIG_FSL_DIU_FB
- Enable the Freescale DIU video driver. Reference boards for
- SOCs that have a DIU should define this macro to enable DIU
- support, and should also define these other macros:
-
- CONFIG_SYS_DIU_ADDR
- CONFIG_VIDEO
- CONFIG_CFB_CONSOLE
- CONFIG_VIDEO_SW_CURSOR
- CONFIG_VGA_AS_SINGLE_DEVICE
- CONFIG_VIDEO_BMP_LOGO
-
- The DIU driver will look for the 'video-mode' environment
- variable, and if defined, enable the DIU as a console during
- boot. See the documentation file doc/README.video for a
- description of this variable.
-
- LCD Support: CONFIG_LCD
Define this to enable LCD support (for output to LCD
display); also select one of the supported displays
by defining one of these:
- CONFIG_ATMEL_LCD:
-
- HITACHI TX09D70VM1CCA, 3.5", 240x320.
-
CONFIG_NEC_NL6448AC33:
NEC NL6448AC33-18. Active, color, single scan.
If CONFIG_LCD_ROTATION is not defined, the console will be
initialized with 0degree rotation.
- CONFIG_LCD_BMP_RLE8
-
- Support drawing of RLE8-compressed bitmaps on the LCD.
-
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
The clock frequency of the MII bus
- CONFIG_PHY_RESET_DELAY
-
- Some PHY like Intel LXT971A need extra delay after
- reset before any MII register access is possible.
- For such PHY, set this option to the usec delay
- required. (minimum 300usec for LXT971A)
-
CONFIG_PHY_CMD_DELAY (ppc4xx)
Some PHY like Intel LXT971A need extra delay after
of the backslashes before semicolons and special
symbols.
-- Command Line Editing and History:
- CONFIG_CMDLINE_PS_SUPPORT
-
- Enable support for changing the command prompt string
- at run-time. Only static string is supported so far.
- The string is obtained from environment variables PS1
- and PS2.
-
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_MAX_FOOTPRINT
- Maximum size in memory allocated to the SPL, BSS included.
- When defined, the linker checks that the actual memory
- used by SPL from _start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_MAX_SIZE
- Maximum size of the SPL image (text, data, rodata, and
- linker lists sections), BSS excluded.
- When defined, the linker checks that the actual size does
- not exceed it.
-
CONFIG_SPL_RELOC_TEXT_BASE
Address to relocate to. If unspecified, this is equal to
CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
CONFIG_SPL_BSS_START_ADDR
Link address for the BSS within the SPL binary.
- CONFIG_SPL_BSS_MAX_SIZE
- Maximum size in memory allocated to the SPL BSS.
- When defined, the linker checks that the actual memory used
- by SPL from __bss_start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_STACK
- Adress of the start of the stack SPL will use
-
CONFIG_SPL_PANIC_ON_RAW_IMAGE
When defined, SPL will panic() if the image it has
loaded does not have a signature.
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
- CONFIG_SPL_STACK.
-
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
When this option is set the full malloc is used in SPL and
For ARM, enable an optional function to print more information
about the running system.
- CONFIG_SPL_INIT_MINIMAL
- Arch init code should be built for a very small image
-
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
Sector and number of sectors to load kernel argument
parameters from when MMC is being used in raw mode
(for falcon mode)
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- Filename to read to load U-Boot when reading from filesystem
-
- CONFIG_SPL_FS_LOAD_KERNEL_NAME
- Filename to read to load kernel uImage when reading
- from filesystem (for Falcon mode)
-
- CONFIG_SPL_FS_LOAD_ARGS_NAME
- Filename to read to load kernel argument parameters
- when reading from filesystem (for Falcon mode)
-
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
start.S waits for the rest of the SPL to load before
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
- CONFIG_SPL_SKIP_RELOCATE
- Avoid SPL relocation
-
CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SPL_NAND_RAW_ONLY
- Support to boot only raw u-boot.bin images. Use this only
- if you need to save space.
-
- CONFIG_SPL_COMMON_INIT_DDR
- Set for common ddr init with serial presence detect in
- SPL binary.
-
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SPL_PAD_TO
- Image offset to which the SPL should be padded before appending
- the SPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
use an arch-specific makefile fragment instead, for
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
-- TPL framework
- CONFIG_TPL
- Enable building of TPL globally.
-
- CONFIG_TPL_PAD_TO
- Image offset to which the TPL should be padded before appending
- the TPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
-- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
-
-- CONFIG_SYS_PBSIZE: Buffer size for Console output
-
-- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
-
-- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
- the application (usually a Linux kernel) when it is
- booted
-
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_MEM_TOP_HIDE:
- If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
- this specified memory area will get subtracted from the top
- (end) of RAM and won't get "touched" at all by U-Boot. By
- fixing up gd->ram_size the Linux kernel should gets passed
- the now "corrected" memory size and won't touch it either.
- This should work for arch/ppc and arch/powerpc. Only Linux
- board ports in arch/powerpc with bootwrapper support that
- recalculate the memory size from the SDRAM controller setup
- will have to get fixed in Linux additionally.
-
- This option can be used as a workaround for the 440EPx/GRx
- CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
- be touched.
-
- WARNING: Please make sure that this value is a multiple of
- the Linux page size (normally 4k). If this is not the case,
- then the end address of the Linux memory will be located at a
- non page size aligned address and this could cause major
- problems.
-
- CONFIG_SYS_LOADS_BAUD_CHANGE:
Enable temporary baudrate change while serial download
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
-- CONFIG_SYS_MONITOR_BASE:
- Physical start address of boot monitor code (set by
- make config files to be same as the text base address
- (CONFIG_SYS_TEXT_BASE) used when linking) - same as
- CONFIG_SYS_FLASH_BASE when booting from flash.
-
- CONFIG_SYS_MONITOR_LEN:
Size of memory reserved for monitor code, used to
determine _at_compile_time_ (!) if the environment is
while unprotecting/erasing/programming. Please only enable
this option if you really know what you are doing.
-- CONFIG_SYS_RX_ETH_BUFFER:
- Defines the number of Ethernet receive buffers. On some
- Ethernet controllers it is recommended to set this value
- to 8 or even higher (EEPRO100 or 405 EMAC), since all
- buffers can be full shortly after enabling the interface
- on high Ethernet traffic.
- Defaults to 4 if not defined.
-
- CONFIG_ENV_MAX_ENTRIES
Maximum number of entries in the hash table that is used
later, once stdio is running and output goes to the LCD, if
present.
-- CONFIG_BOARD_SIZE_LIMIT:
- Maximum size of the U-Boot image. When defined, the
- build system checks that the actual size does not
- exceed it.
-
Low Level (hardware related) configuration options:
---------------------------------------------------
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
- If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
- forced to a value that ensures that CCSR is not relocated.
-
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
-- CONFIG_SYS_GBL_DATA_OFFSET:
-
- Offset of the initial data structure in the memory
- area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
- CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
- data is located at the end of the available space
- (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- GENERATED_GBL_DATA_SIZE), and the initial stack is just
- below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
- CONFIG_SYS_GBL_DATA_OFFSET) downward.
-
- Note:
- On the MPC824X (or other systems that use the data
- cache for initial memory) the address chosen for
- CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
- point to an otherwise UNUSED address space between
- the top of RAM and the start of the PCI space.
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, INTEGRITY).
* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
- IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
- Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
+ IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+ Currently supported: ARM, Intel x86, MIPS, Nios II, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
Note: on Nios II, we give "-G0" option to gcc and don't use gp
to access small data sections, so gp is free.
-On NDS32, the following registers are used:
-
- R0-R1: argument/return
- R2-R5: argument
- R15: temporary register for assembler
- R16: trampoline register
- R28: frame pointer (FP)
- R29: global pointer (GP)
- R30: link register (LP)
- R31: stack pointer (SP)
- PC: program counter (PC)
-
- ==> U-Boot will use R10 to hold a pointer to the global data
-
-NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
-or current versions of GCC may "optimize" the code too much.
-
On RISC-V, the following registers are used:
x0: hard-wired zero (zero)
projects / platform / kernel / u-boot.git / blobdiff