bloblist: Correct condition in bloblist_addrec()

[platform/kernel/u-boot.git] / README

diff --git a/README b/README
index 5ca11f2..1472b40 100644 (file)
--- a/README
+++ b/README
@@ -58,8 +58,8 @@ Where to get source code:
 =========================
 
 The U-Boot source code is maintained in the Git repository at
-https://gitlab.denx.de/u-boot/u-boot.git ; you can browse it online at
-https://gitlab.denx.de/u-boot/u-boot
+https://source.denx.de/u-boot/u-boot.git ; you can browse it online at
+https://source.denx.de/u-boot/u-boot
 
 The "Tags" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
@@ -423,8 +423,7 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR
                Freescale DDR driver in use. This type of DDR controller is
-               found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
-               SoCs.
+               found in mpc83xx, mpc85xx as well as some ARM core SoCs.
 
                CONFIG_SYS_FSL_DDR_ADDR
                Freescale DDR memory-mapped register base.
@@ -575,7 +574,6 @@ The following options need to be configured:
                 * The bootm command automatically updates the fdt
 
                OF_TBCLK - The timebase frequency.
-               OF_STDOUT_PATH - The path to the console device
 
                boards with QUICC Engines require OF_QE to set UCC MAC
                addresses
@@ -631,10 +629,6 @@ The following options need to be configured:
                                        controller register space
 
 - Serial Ports:
-               CONFIG_PL010_SERIAL
-
-               Define this if you want support for Amba PrimeCell PL010 UARTs.
-
                CONFIG_PL011_SERIAL
 
                Define this if you want support for Amba PrimeCell PL011 UARTs.
@@ -748,6 +742,15 @@ The following options need to be configured:
                SoC, then define this variable and provide board
                specific code for the "hw_watchdog_reset" function.
 
+               CONFIG_SYS_WATCHDOG_FREQ
+               Some platforms automatically call WATCHDOG_RESET()
+               from the timer interrupt handler every
+               CONFIG_SYS_WATCHDOG_FREQ interrupts. If not set by the
+               board configuration file, a default of CONFIG_SYS_HZ/2
+               (i.e. 500) is used. Setting CONFIG_SYS_WATCHDOG_FREQ
+               to 0 disables calling WATCHDOG_RESET() from the timer
+               interrupt.
+
 - Real-Time Clock:
 
                When CONFIG_CMD_DATE is selected, the type of the RTC
@@ -2770,13 +2773,6 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
                Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 
-- CONFIG_PCI_ENUM_ONLY
-               Only scan through and get the devices on the buses.
-               Don't do any setup work, presumably because someone or
-               something has already done it, and we don't need to do it
-               a second time.  Useful for platforms that are pre-booted
-               by coreboot or similar.
-
 - CONFIG_PCI_INDIRECT_BRIDGE:
                Enable support for indirect PCI bridges.
 
@@ -3153,6 +3149,7 @@ i2c       - I2C sub-system
 sspi   - SPI utility commands
 base   - print or set address offset
 printenv- print environment variables
+pwm    - control pwm channels
 setenv - set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection