RISC-V: Support CPUID for risc-v in perf

[platform/kernel/linux-starfive.git] / MAINTAINERS

diff --git a/MAINTAINERS b/MAINTAINERS
index 95a1d9d..3815c47 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16094,6 +16094,15 @@ S:     Maintained
 F:     drivers/mtd/nand/raw/r852.c
 F:     drivers/mtd/nand/raw/r852.h
 
+RISC-V PMU DRIVERS
+M:     Atish Patra <atishp@atishpatra.org>
+R:     Anup Patel <anup@brainfault.org>
+L:     linux-riscv@lists.infradead.org
+S:     Supported
+F:     drivers/perf/riscv_pmu.c
+F:     drivers/perf/riscv_pmu_legacy.c
+F:     drivers/perf/riscv_pmu_sbi.c
+
 RISC-V ARCHITECTURE
 M:     Paul Walmsley <paul.walmsley@sifive.com>
 M:     Palmer Dabbelt <palmer@dabbelt.com>
@@ -20847,3 +20856,12 @@ M:     Jianlong Huang <jianlong.huang@starfivetech.com>
 S:     Maintained
 F:     Documentation/devicetree/bindings/riscv/starfive-jh7110.yaml
 
+STARFIVE JH7110 PINCTRL
+M:     Jianlong Huang <jianlong.huang@starfivetech.com>
+S:     Maintained
+F:     Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
+
+STARFIVE JH7110 SDIO
+M:     William Qiu <william.qiu@starfivetech.com>
+S:     Maintained
+F:     Documentation/devicetree/bindings/mmc/starfive,jh7110-sdio.yaml