+2015-01-31 David S. Miller <davem@davemloft.net>
+
+ * sysdeps/sparc/sparc32/bits/atomic.h
+ (__sparc32_atomic_do_unlock24): Put the memory barrier before the
+ unlock not after it.
+ (__v9_compare_and_exchange_val_32_acq): Use unions to avoid getting
+ volatile register usage warnings from the compiler.
+
+ * sysdeps/sparc/nptl/sem_init.c: Delete.
+ * sysdeps/sparc/nptl/sem_post.c: Delete.
+ * sysdeps/sparc/nptl/sem_timedwait.c: Delete.
+ * sysdeps/sparc/nptl/sem_wait.c: Delete.
+ * sysdeps/sparc/sparc32/sem_init.c: New file.
+ * sysdeps/sparc/sparc32/sem_waitcommon.c: New file.
+ * sysdeps/sparc/sparc32/sem_open.c: Generic nptl version with
+ padding explicitly initialized.
+ * sysdeps/sparc/sparc32/sem_post.c: Generic nptl version using
+ padding for in-semaphore spinlock.
+ * sysdeps/sparc/sparc32/sem_wait.c: Likewise.
+ * sysdeps/sparc/sparc32/sem_trywait.c: Delete.
+ * sysdeps/sparc/sparc32/sem_timedwait.c: Delete.
+ * sysdeps/sparc/sparc32/sparcv9/sem_init.c: New file.
+ * sysdeps/sparc/sparc32/sparcv9/sem_open.c: New file.
+ * sysdeps/sparc/sparc32/sparcv9/sem_post.c: New file.
+ * sysdeps/sparc/sparc32/sparcv9/sem_waitcommon.c: New file.
+ * sysdeps/sparc/sparc32/sparcv9/sem_wait.c: Redirect to nptl
+ version.
+ * sysdeps/sparc/sparc32/sparcv9/sem_timedwait.c: Delete.
+ * sysdeps/sparc/sparc32/sparcv9/sem_trywait.c: Delete.
+
+2015-01-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ [BZ #17801]
+ * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
+ Set the bit_AVX_Fast_Unaligned_Load bit for AVX2.
+ * sysdeps/x86_64/multiarch/init-arch.h (bit_AVX_Fast_Unaligned_Load):
+ New.
+ (index_AVX_Fast_Unaligned_Load): Likewise.
+ (HAS_AVX_FAST_UNALIGNED_LOAD): Likewise.
+ * sysdeps/x86_64/multiarch/memcpy.S (__new_memcpy): Check the
+ bit_AVX_Fast_Unaligned_Load bit instead of the bit_AVX_Usable bit.
+ * sysdeps/x86_64/multiarch/memcpy_chk.S (__memcpy_chk): Likewise.
+ * sysdeps/x86_64/multiarch/mempcpy.S (__mempcpy): Likewise.
+ * sysdeps/x86_64/multiarch/mempcpy_chk.S (__mempcpy_chk): Likewise.
+ * sysdeps/x86_64/multiarch/memmove.c (__libc_memmove): Replace
+ HAS_AVX with HAS_AVX_FAST_UNALIGNED_LOAD.
+ * sysdeps/x86_64/multiarch/memmove_chk.c (__memmove_chk): Likewise.
+
+2015-01-29 Andreas Schwab <schwab@suse.de>
+
+ * sysdeps/nptl/allocrtsig.c: Include <signal.h>.
+
+2015-01-29 Siddhesh Poyarekar <siddhesh@redhat.com>
+
+ [BZ #17892]
+ * nscd/nscd_stat.c (send_stats): Initialize DATA.
+
+2015-01-28 Martin Sebor <msebor@redhat.com>
+
+ * math/README.libm-test: Clarify. Add "How to read the test output."
+
+2015-01-28 Chris Metcalf <cmetcalf@ezchip.com>
+
+ * sysdeps/tile/tilegx/bits/atomic.h [!_LP64] (__HAVE_64B_ATOMICS):
+ Define to 0.
+
+2015-01-28 Joseph Myers <joseph@codesourcery.com>
+
+ * sysdeps/mips/bits/atomic.h [_MIPS_SIM == _ABIN32]
+ (__HAVE_64B_ATOMICS): Define to 0.
+
+2015-01-28 Adhemerval Zanellla <azanella@linux.vnet.ibm.com>
+
+ [BZ #17885]
+ * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Fix correct
+ value to set as new flag.
+
+ [BZ #16576]
+ * sysdeps/powerpc/fpu/math_private.h [__CPU_HAS_FSQRT]: Remove define
+ and use _ARCH_PPCSQ instead.
+ (__ieee754_sqrt): Likewise.
+ (__ieee754_sqrtf): Likewise.
+ * sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Build only if
+ _ARCH_PPCSQ is defined.
+ (__ieee754_sqrt): Use _ARCH_PPCSQ to select wheter to use hardware
+ fsqrt instruction.
+ * sysdeps/powerpc/fpu/e_sqrtf.c (__ieee754_sqrtf): Build only if
+ _ARCH_PPCSQ is defined.
+ (__ieee754_sqrtf): Use _ARCH_PPCSQ to select wheter to use hardware
+ fsqrts instruction.
+ * sysdeps/powerpc/powerpc64/fpu/e_sqrt.c: Remove file.
+
+2015-01-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * iconv/loop.c: Suppress array out of bound warning caused by GCC
+ bug (GCC BZ #64739).
+
2015-01-25 Andreas Schwab <schwab@linux-m68k.org>
+ * sysdeps/unix/sysv/linux/ia64/lowlevellock.h (lll_futex_requeue):
+ Mark _retval as used.
+ (lll_futex_wake_unlock): Likewise.
+ (lll_futex_timed_wait_requeue_pi): Likewise.
+
* sysdeps/unix/sysv/linux/m68k/coldfire/bits/atomic.h
(atomic_compare_and_exchange_val_acq): Use uint32_t for the
register variables.
(R_NIOS2_CACHE_OPX,R_NIOS2_IMM6,R_NIOS2_IMM8,R_NIOS2_HI16): Likewise.
(R_NIOS2_LO16,R_NIOS2_HIADJ16,R_NIOS2_BFD_RELOC_32): Likewise.
(R_NIOS2_BFD_RELOC_16,R_NIOS2_BFD_RELOC_8,R_NIOS2_GPREL): Likewise.
- (R_NIOS2_GNU_VTINHERIT,R_NIOS2_GNU_VTENTRY,R_NIOS2_UJMP): Likewise.
- (R_NIOS2_CJMP,R_NIOS2_CALLR,R_NIOS2_ALIGN,R_NIOS2_GOT16): Likewise.
- (R_NIOS2_CALL16,R_NIOS2_GOTOFF_LO,R_NIOS2_GOTOFF_HA): Likewise.
- (R_NIOS2_PCREL_LO,R_NIOS2_PCREL_HA,R_NIOS2_TLS_GD16): Likewise.
- (R_NIOS2_TLS_LDM16,R_NIOS2_TLS_LDO16,R_NIOS2_TLS_IE16): Likewise.
- (R_NIOS2_TLS_LE16,R_NIOS2_TLS_DTPMOD,R_NIOS2_TLS_DTPREL): Likewise.
+ (R_NIOS2_GNU_VTINHERIT,R_NIOS2_GNU_VTENTRY,R_NIOS2_UJMP): Likewise.
+ (R_NIOS2_CJMP,R_NIOS2_CALLR,R_NIOS2_ALIGN,R_NIOS2_GOT16): Likewise.
+ (R_NIOS2_CALL16,R_NIOS2_GOTOFF_LO,R_NIOS2_GOTOFF_HA): Likewise.
+ (R_NIOS2_PCREL_LO,R_NIOS2_PCREL_HA,R_NIOS2_TLS_GD16): Likewise.
+ (R_NIOS2_TLS_LDM16,R_NIOS2_TLS_LDO16,R_NIOS2_TLS_IE16): Likewise.
+ (R_NIOS2_TLS_LE16,R_NIOS2_TLS_DTPMOD,R_NIOS2_TLS_DTPREL): Likewise.
(R_NIOS2_TLS_TPREL,R_NIOS2_COPY,R_NIOS2_GLOB_DAT): Likewise.
(R_NIOS2_JUMP_SLOT,R_NIOS2_RELATIVE,R_NIOS2_GOTOFF): Likewise.
(R_NIOS2_CALL26_NOAT,R_NIOS2_GOT_LO,R_NIOS2_GOT_HA): Likewise.
2015-01-05 Chris Metcalf <cmetcalf@ezchip.com>
- * sysdeps/unix/sysv/linux/tile/bits/libc-vdso.h: Fix return type
- for __vdso_* functions in declarations.
- * sysdeps/unix/sysv/linux/tile/init-first.c: Likewise for
- definitions.
- * sysdeps/unix/sysv/linux/tile/sysdep.h (INLINE_VSYSCALL,
- INTERNAL_VSYSCALL): Use struct return types to check for error.
+ * sysdeps/unix/sysv/linux/tile/bits/libc-vdso.h: Fix return type
+ for __vdso_* functions in declarations.
+ * sysdeps/unix/sysv/linux/tile/init-first.c: Likewise for
+ definitions.
+ * sysdeps/unix/sysv/linux/tile/sysdep.h (INLINE_VSYSCALL,
+ INTERNAL_VSYSCALL): Use struct return types to check for error.
* sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c [!defined _LP64
&& REGISTER_CAST_INT32_TO_INT64]: Provide explicit lround()