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Prepare for 64bit relocation addresses
[platform/upstream/intel-gpu-tools.git]
/
tests
/
gem_caching.c
diff --git
a/tests/gem_caching.c
b/tests/gem_caching.c
index
6c1d941
..
ddd7d94
100644
(file)
--- a/
tests/gem_caching.c
+++ b/
tests/gem_caching.c
@@
-34,12
+34,16
@@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
+#include <drm.h>
+
+#include "ioctl_wrappers.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
/*
* Testcase: snoop consistency when touching partial cachelines
/*
* Testcase: snoop consistency when touching partial cachelines
@@
-59,10
+63,7
@@
int fd;
static void
copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
{
static void
copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
{
- BEGIN_BATCH(8);
- OUT_BATCH(XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB);
+ BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
4096);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
4096);
@@
-103,14
+104,13
@@
blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
#define TEST_READ 0x1
#define TEST_WRITE 0x2
#define TEST_BOTH (TEST_READ | TEST_WRITE)
#define TEST_READ 0x1
#define TEST_WRITE 0x2
#define TEST_BOTH (TEST_READ | TEST_WRITE)
-i
nt main(int argc, char **argv)
+i
gt_main
{
unsigned flags = TEST_BOTH;
int i, j;
uint8_t *cpu_ptr;
uint8_t *gtt_ptr;
{
unsigned flags = TEST_BOTH;
int i, j;
uint8_t *cpu_ptr;
uint8_t *gtt_ptr;
- igt_subtest_init(argc, argv);
igt_skip_on_simulation();
igt_fixture {
igt_skip_on_simulation();
igt_fixture {
@@
-125,7
+125,7
@@
int main(int argc, char **argv)
flags &= ~TEST_READ;
if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
/* chipset is completely fubar */
flags &= ~TEST_READ;
if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
/* chipset is completely fubar */
-
printf
("coherency broken on i965g/gm\n");
+
igt_info
("coherency broken on i965g/gm\n");
flags = 0;
}
flags = 0;
}
@@
-145,7
+145,7
@@
int main(int argc, char **argv)
igt_subtest("reads") {
igt_require(flags & TEST_READ);
igt_subtest("reads") {
igt_require(flags & TEST_READ);
-
printf
("checking partial reads\n");
+
igt_info
("checking partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i;
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i;
@@
-172,7
+172,7
@@
int main(int argc, char **argv)
igt_subtest("writes") {
igt_require(flags & TEST_WRITE);
igt_subtest("writes") {
igt_require(flags & TEST_WRITE);
-
printf
("checking partial writes\n");
+
igt_info
("checking partial writes\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1;
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1;
@@
-217,7
+217,7
@@
int main(int argc, char **argv)
igt_subtest("read-writes") {
igt_require((flags & TEST_BOTH) == TEST_BOTH);
igt_subtest("read-writes") {
igt_require((flags & TEST_BOTH) == TEST_BOTH);
-
printf
("checking partial writes after partial reads\n");
+
igt_info
("checking partial writes after partial reads\n");
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1, val2;
for (i = 0; i < ROUNDS; i++) {
uint8_t val0 = i, val1, val2;
@@
-284,6
+284,4
@@
int main(int argc, char **argv)
close(fd);
}
close(fd);
}
-
- igt_exit();
}
}