+ cacheSize = std::max(cacheSize, (size_t)sysconf(_SC_LEVEL4_CACHE_SIZE));
+#endif
+
+#if defined(_ARM64_)
+ if(cacheSize == 0)
+ {
+ size_t size;
+
+ if(ReadMemoryValueFromFile("/sys/devices/system/cpu/cpu0/cache/index0/size", &size))
+ cacheSize = std::max(cacheSize, size);
+ if(ReadMemoryValueFromFile("/sys/devices/system/cpu/cpu0/cache/index1/size", &size))
+ cacheSize = std::max(cacheSize, size);
+ if(ReadMemoryValueFromFile("/sys/devices/system/cpu/cpu0/cache/index2/size", &size))
+ cacheSize = std::max(cacheSize, size);
+ if(ReadMemoryValueFromFile("/sys/devices/system/cpu/cpu0/cache/index3/size", &size))
+ cacheSize = std::max(cacheSize, size);
+ if(ReadMemoryValueFromFile("/sys/devices/system/cpu/cpu0/cache/index4/size", &size))
+ cacheSize = std::max(cacheSize, size);
+ }
+
+ if(cacheSize == 0)
+ {
+ // It is currently expected to be missing cache size info
+ //
+ // _SC_LEVEL*_*CACHE_SIZE is not yet present. Work is in progress to enable this for arm64
+ //
+ // /sys/devices/system/cpu/cpu*/cache/index*/ is also not yet present in most systems.
+ // Arm64 patch is in Linux kernel tip.
+ //
+ // midr_el1 is available in "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1",
+ // but without an exhaustive list of ARM64 processors any decode of midr_el1
+ // Would likely be incomplete
+
+ // Published information on ARM64 architectures is limited.
+ // If we use recent high core count chips as a guide for state of the art, we find
+ // total L3 cache to be 1-2MB/core. As always, there are exceptions.
+
+ // Estimate cache size based on CPU count
+ // Assume lower core count are lighter weight parts which are likely to have smaller caches
+ // Assume L3$/CPU grows linearly from 256K to 1.5M/CPU as logicalCPUs grows from 2 to 12 CPUs
+ DWORD logicalCPUs = PAL_GetLogicalCpuCountFromOS();
+
+ cacheSize = logicalCPUs*std::min(1536, std::max(256, (int)logicalCPUs*128))*1024;
+ }