+ info->use_asm = true; /* we assume a minimum of 80386 with FLAC__CPU_IA32 */
+ info->data.ia32.cpuid = FLAC__cpu_have_cpuid_asm_ia32()? true : false;
+ info->data.ia32.bswap = info->data.ia32.cpuid; /* CPUID => BSWAP since it came after */
+ info->data.ia32.cmov = false;
+ info->data.ia32.mmx = false;
+ info->data.ia32.fxsr = false;
+ info->data.ia32.sse = false;
+ info->data.ia32.sse2 = false;
+ info->data.ia32.sse3 = false;
+ info->data.ia32.ssse3 = false;
+ info->data.ia32._3dnow = false;
+ info->data.ia32.ext3dnow = false;
+ info->data.ia32.extmmx = false;
+ if(info->data.ia32.cpuid) {
+ /* http://www.sandpile.org/ia32/cpuid.htm */
+ FLAC__uint32 flags_edx, flags_ecx;
+ FLAC__cpu_info_asm_ia32(&flags_edx, &flags_ecx);
+ info->data.ia32.cmov = (flags_edx & FLAC__CPUINFO_IA32_CPUID_CMOV )? true : false;
+ info->data.ia32.mmx = (flags_edx & FLAC__CPUINFO_IA32_CPUID_MMX )? true : false;
+ info->data.ia32.fxsr = (flags_edx & FLAC__CPUINFO_IA32_CPUID_FXSR )? true : false;
+ info->data.ia32.sse = (flags_edx & FLAC__CPUINFO_IA32_CPUID_SSE )? true : false;
+ info->data.ia32.sse2 = (flags_edx & FLAC__CPUINFO_IA32_CPUID_SSE2 )? true : false;
+ info->data.ia32.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 )? true : false;
+ info->data.ia32.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false;
+
+#ifdef FLAC__USE_3DNOW
+ flags_edx = FLAC__cpu_info_extended_amd_asm_ia32();
+ info->data.ia32._3dnow = (flags_edx & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_3DNOW )? true : false;
+ info->data.ia32.ext3dnow = (flags_edx & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_EXT3DNOW)? true : false;
+ info->data.ia32.extmmx = (flags_edx & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_EXTMMX )? true : false;
+#else
+ info->data.ia32._3dnow = info->data.ia32.ext3dnow = info->data.ia32.extmmx = false;
+#endif
+
+#ifdef DEBUG
+ fprintf(stderr, "CPU info (IA-32):\n");
+ fprintf(stderr, " CPUID ...... %c\n", info->data.ia32.cpuid ? 'Y' : 'n');
+ fprintf(stderr, " BSWAP ...... %c\n", info->data.ia32.bswap ? 'Y' : 'n');
+ fprintf(stderr, " CMOV ....... %c\n", info->data.ia32.cmov ? 'Y' : 'n');
+ fprintf(stderr, " MMX ........ %c\n", info->data.ia32.mmx ? 'Y' : 'n');
+ fprintf(stderr, " FXSR ....... %c\n", info->data.ia32.fxsr ? 'Y' : 'n');
+ fprintf(stderr, " SSE ........ %c\n", info->data.ia32.sse ? 'Y' : 'n');
+ fprintf(stderr, " SSE2 ....... %c\n", info->data.ia32.sse2 ? 'Y' : 'n');
+ fprintf(stderr, " SSE3 ....... %c\n", info->data.ia32.sse3 ? 'Y' : 'n');
+ fprintf(stderr, " SSSE3 ...... %c\n", info->data.ia32.ssse3 ? 'Y' : 'n');
+ fprintf(stderr, " 3DNow! ..... %c\n", info->data.ia32._3dnow ? 'Y' : 'n');
+ fprintf(stderr, " 3DNow!-ext . %c\n", info->data.ia32.ext3dnow? 'Y' : 'n');
+ fprintf(stderr, " 3DNow!-MMX . %c\n", info->data.ia32.extmmx ? 'Y' : 'n');
+#endif
+
+ /*
+ * now have to check for OS support of SSE/SSE2
+ */
+ if(info->data.ia32.fxsr || info->data.ia32.sse || info->data.ia32.sse2) {
+#if defined FLAC__NO_SSE_OS
+ /* assume user knows better than us; turn it off */
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+#elif defined FLAC__SSE_OS
+ /* assume user knows better than us; leave as detected above */
+#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
+ int sse = 0;
+ size_t len;
+ /* at least one of these must work: */
+ len = sizeof(sse); sse = sse || (sysctlbyname("hw.instruction_sse", &sse, &len, NULL, 0) == 0 && sse);
+ len = sizeof(sse); sse = sse || (sysctlbyname("hw.optional.sse" , &sse, &len, NULL, 0) == 0 && sse); /* __APPLE__ ? */
+ if(!sse)
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+#elif defined(__NetBSD__) || defined (__OpenBSD__)
+# if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
+ int val = 0, mib[2] = { CTL_MACHDEP, CPU_SSE };
+ size_t len = sizeof(val);
+ if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val)
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+ else { /* double-check SSE2 */
+ mib[1] = CPU_SSE2;
+ len = sizeof(val);
+ if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val)
+ info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+ }
+# else
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+# endif
+#elif defined(__linux__)
+ int sse = 0;
+ struct sigaction sigill_save;
+#ifdef USE_OBSOLETE_SIGCONTEXT_FLAVOR
+ if(0 == sigaction(SIGILL, NULL, &sigill_save) && signal(SIGILL, (void (*)(int))sigill_handler_sse_os) != SIG_ERR)
+#else
+ struct sigaction sigill_sse;
+ sigill_sse.sa_sigaction = sigill_handler_sse_os;
+ __sigemptyset(&sigill_sse.sa_mask);
+ sigill_sse.sa_flags = SA_SIGINFO | SA_RESETHAND; /* SA_RESETHAND just in case our SIGILL return jump breaks, so we don't get stuck in a loop */
+ if(0 == sigaction(SIGILL, &sigill_sse, &sigill_save))
+#endif
+ {
+ /* http://www.ibiblio.org/gferg/ldp/GCC-Inline-Assembly-HOWTO.html */
+ /* see sigill_handler_sse_os() for an explanation of the following: */
+ asm volatile (
+ "xorl %0,%0\n\t" /* for some reason, still need to do this to clear 'sse' var */
+ "xorps %%xmm0,%%xmm0\n\t" /* will cause SIGILL if unsupported by OS */
+ "incl %0\n\t" /* SIGILL handler will jump over this */
+ /* landing zone */
+ "nop\n\t" /* SIGILL jump lands here if "inc" is 9 bytes */
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t" /* SIGILL jump lands here if "inc" is 3 bytes (expected) */
+ "nop\n\t"
+ "nop" /* SIGILL jump lands here if "inc" is 1 byte */
+ : "=r"(sse)
+ : "r"(sse)
+ );
+
+ sigaction(SIGILL, &sigill_save, NULL);
+ }
+
+ if(!sse)
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+#elif defined(_MSC_VER)
+# ifdef USE_TRY_CATCH_FLAVOR
+ _try {
+ __asm {
+# if _MSC_VER <= 1200
+ /* VC6 assembler doesn't know SSE, have to emit bytecode instead */
+ _emit 0x0F
+ _emit 0x57
+ _emit 0xC0
+# else
+ xorps xmm0,xmm0
+# endif
+ }
+ }
+ _except(EXCEPTION_EXECUTE_HANDLER) {
+ if (_exception_code() == STATUS_ILLEGAL_INSTRUCTION)
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+ }
+# else
+ int sse = 0;
+ LPTOP_LEVEL_EXCEPTION_FILTER save = SetUnhandledExceptionFilter(sigill_handler_sse_os);
+ /* see GCC version above for explanation */
+ /* http://msdn2.microsoft.com/en-us/library/4ks26t93.aspx */
+ /* http://www.codeproject.com/cpp/gccasm.asp */
+ /* http://www.hick.org/~mmiller/msvc_inline_asm.html */
+ __asm {
+# if _MSC_VER <= 1200
+ /* VC6 assembler doesn't know SSE, have to emit bytecode instead */
+ _emit 0x0F
+ _emit 0x57
+ _emit 0xC0
+# else
+ xorps xmm0,xmm0
+# endif
+ inc sse
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ }
+ SetUnhandledExceptionFilter(save);
+ if(!sse)
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
+# endif
+#else
+ /* no way to test, disable to be safe */
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;