[AArch64] Enable CRC feature in GAS for cortex-a53 and cortex-a57.

[platform/upstream/binutils.git] / opcodes / i386-dis.c

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index a4e16cb..ebd8f41 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1,7 +1,5 @@
 /* Print i386 instructions for GDB, the GNU debugger.
 /* Print i386 instructions for GDB, the GNU debugger.

-   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
-   Free Software Foundation, Inc.
+   Copyright (C) 1988-2014 Free Software Foundation, Inc.

 
    This file is part of the GNU opcodes library.
 
 
    This file is part of the GNU opcodes library.
 


@@ -94,11 +92,13 @@ static void OP_EX_VexW (int, int);
 static void OP_EX_VexImmW (int, int);
 static void OP_XMM_Vex (int, int);
 static void OP_XMM_VexW (int, int);
 static void OP_EX_VexImmW (int, int);
 static void OP_XMM_Vex (int, int);
 static void OP_XMM_VexW (int, int);

+static void OP_Rounding (int, int);

 static void OP_REG_VexI4 (int, int);
 static void PCLMUL_Fixup (int, int);
 static void VEXI4_Fixup (int, int);
 static void VZERO_Fixup (int, int);
 static void VCMP_Fixup (int, int);
 static void OP_REG_VexI4 (int, int);
 static void PCLMUL_Fixup (int, int);
 static void VEXI4_Fixup (int, int);
 static void VZERO_Fixup (int, int);
 static void VCMP_Fixup (int, int);

+static void VPCMP_Fixup (int, int);

 static void OP_0f07 (int, int);
 static void OP_Monitor (int, int);
 static void OP_Mwait (int, int);
 static void OP_0f07 (int, int);
 static void OP_Monitor (int, int);
 static void OP_Mwait (int, int);


@@ -108,6 +108,10 @@ static void OP_3DNowSuffix (int, int);
 static void CMP_Fixup (int, int);
 static void BadOp (void);
 static void REP_Fixup (int, int);
 static void CMP_Fixup (int, int);
 static void BadOp (void);
 static void REP_Fixup (int, int);

+static void BND_Fixup (int, int);
+static void HLE_Fixup1 (int, int);
+static void HLE_Fixup2 (int, int);
+static void HLE_Fixup3 (int, int);

 static void CMPXCHG8B_Fixup (int, int);
 static void XMM_Fixup (int, int);
 static void CRC32_Fixup (int, int);
 static void CMPXCHG8B_Fixup (int, int);
 static void XMM_Fixup (int, int);
 static void CRC32_Fixup (int, int);


@@ -119,13 +123,15 @@ static void OP_Vex_2src_2 (int, int);
 
 static void MOVBE_Fixup (int, int);
 
 
 static void MOVBE_Fixup (int, int);
 

+static void OP_Mask (int, int);
+

 struct dis_private {
   /* Points to first byte not fetched.  */
   bfd_byte *max_fetched;
   bfd_byte the_buffer[MAX_MNEM_SIZE];
   bfd_vma insn_start;
   int orig_sizeflag;
 struct dis_private {
   /* Points to first byte not fetched.  */
   bfd_byte *max_fetched;
   bfd_byte the_buffer[MAX_MNEM_SIZE];
   bfd_vma insn_start;
   int orig_sizeflag;

-  jmp_buf bailout;
+  OPCODES_SIGJMP_BUF bailout;

 };
 
 enum address_mode
 };
 
 enum address_mode


@@ -208,7 +214,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
         STATUS.  */
       if (priv->max_fetched == priv->the_buffer)
        (*info->memory_error_func) (status, start, info);
         STATUS.  */
       if (priv->max_fetched == priv->the_buffer)
        (*info->memory_error_func) (status, start, info);

-      longjmp (priv->bailout, 1);
+      OPCODES_SIGLONGJMP (priv->bailout, 1);

     }
   else
     priv->max_fetched = addr;
     }
   else
     priv->max_fetched = addr;


@@ -219,13 +225,18 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Bad_Opcode NULL, { { NULL, 0 } }
 
 #define Eb { OP_E, b_mode }
 #define Bad_Opcode NULL, { { NULL, 0 } }
 
 #define Eb { OP_E, b_mode }

+#define Ebnd { OP_E, bnd_mode }

 #define EbS { OP_E, b_swap_mode }
 #define Ev { OP_E, v_mode }
 #define EbS { OP_E, b_swap_mode }
 #define Ev { OP_E, v_mode }

+#define Ev_bnd { OP_E, v_bnd_mode }

 #define EvS { OP_E, v_swap_mode }
 #define Ed { OP_E, d_mode }
 #define Edq { OP_E, dq_mode }
 #define Edqw { OP_E, dqw_mode }
 #define EvS { OP_E, v_swap_mode }
 #define Ed { OP_E, d_mode }
 #define Edq { OP_E, dq_mode }
 #define Edqw { OP_E, dqw_mode }

+#define EdqwS { OP_E, dqw_swap_mode }

 #define Edqb { OP_E, dqb_mode }
 #define Edqb { OP_E, dqb_mode }

+#define Edb { OP_E, db_mode }
+#define Edw { OP_E, dw_mode }

 #define Edqd { OP_E, dqd_mode }
 #define Eq { OP_E, q_mode }
 #define indirEv { OP_indirE, stack_v_mode }
 #define Edqd { OP_E, dqd_mode }
 #define Eq { OP_E, q_mode }
 #define indirEv { OP_indirE, stack_v_mode }


@@ -243,17 +254,20 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Mx { OP_M, x_mode }
 #define Mxmm { OP_M, xmm_mode }
 #define Gb { OP_G, b_mode }
 #define Mx { OP_M, x_mode }
 #define Mxmm { OP_M, xmm_mode }
 #define Gb { OP_G, b_mode }

+#define Gbnd { OP_G, bnd_mode }

 #define Gv { OP_G, v_mode }
 #define Gd { OP_G, d_mode }
 #define Gdq { OP_G, dq_mode }
 #define Gm { OP_G, m_mode }
 #define Gw { OP_G, w_mode }
 #define Rd { OP_R, d_mode }
 #define Gv { OP_G, v_mode }
 #define Gd { OP_G, d_mode }
 #define Gdq { OP_G, dq_mode }
 #define Gm { OP_G, m_mode }
 #define Gw { OP_G, w_mode }
 #define Rd { OP_R, d_mode }

+#define Rdq { OP_R, dq_mode }

 #define Rm { OP_R, m_mode }
 #define Ib { OP_I, b_mode }
 #define sIb { OP_sI, b_mode }  /* sign extened byte */
 #define Rm { OP_R, m_mode }
 #define Ib { OP_I, b_mode }
 #define sIb { OP_sI, b_mode }  /* sign extened byte */

+#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */

 #define Iv { OP_I, v_mode }
 #define Iv { OP_I, v_mode }

-#define sIv { OP_sI, v_mode } 
+#define sIv { OP_sI, v_mode }

 #define Iq { OP_I, q_mode }
 #define Iv64 { OP_I64, v_mode }
 #define Iw { OP_I, w_mode }
 #define Iq { OP_I, q_mode }
 #define Iv64 { OP_I64, v_mode }
 #define Iw { OP_I, w_mode }


@@ -335,7 +349,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define MX { OP_MMX, 0 }
 #define XM { OP_XMM, 0 }
 #define XMScalar { OP_XMM, scalar_mode }
 #define MX { OP_MMX, 0 }
 #define XM { OP_XMM, 0 }
 #define XMScalar { OP_XMM, scalar_mode }

+#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }

 #define XMM { OP_XMM, xmm_mode }
 #define XMM { OP_XMM, xmm_mode }

+#define XMxmmq { OP_XMM, xmmq_mode }

 #define EM { OP_EM, v_mode }
 #define EMS { OP_EM, v_swap_mode }
 #define EMd { OP_EM, d_mode }
 #define EM { OP_EM, v_mode }
 #define EMS { OP_EM, v_swap_mode }
 #define EMd { OP_EM, d_mode }


@@ -344,6 +360,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define EXd { OP_EX, d_mode }
 #define EXdScalar { OP_EX, d_scalar_mode }
 #define EXdS { OP_EX, d_swap_mode }
 #define EXd { OP_EX, d_mode }
 #define EXdScalar { OP_EX, d_scalar_mode }
 #define EXdS { OP_EX, d_swap_mode }

+#define EXdScalarS { OP_EX, d_scalar_swap_mode }

 #define EXq { OP_EX, q_mode }
 #define EXqScalar { OP_EX, q_scalar_mode }
 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 #define EXq { OP_EX, q_mode }
 #define EXqScalar { OP_EX, q_scalar_mode }
 #define EXqScalarS { OP_EX, q_scalar_swap_mode }


@@ -351,10 +368,21 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define EXx { OP_EX, x_mode }
 #define EXxS { OP_EX, x_swap_mode }
 #define EXxmm { OP_EX, xmm_mode }
 #define EXx { OP_EX, x_mode }
 #define EXxS { OP_EX, x_swap_mode }
 #define EXxmm { OP_EX, xmm_mode }

+#define EXymm { OP_EX, ymm_mode }

 #define EXxmmq { OP_EX, xmmq_mode }
 #define EXxmmq { OP_EX, xmmq_mode }

+#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
+#define EXxmm_mb { OP_EX, xmm_mb_mode }
+#define EXxmm_mw { OP_EX, xmm_mw_mode }
+#define EXxmm_md { OP_EX, xmm_md_mode }
+#define EXxmm_mq { OP_EX, xmm_mq_mode }
+#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
+#define EXxmmdw { OP_EX, xmmdw_mode }
+#define EXxmmqd { OP_EX, xmmqd_mode }

 #define EXymmq { OP_EX, ymmq_mode }
 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 #define EXymmq { OP_EX, ymmq_mode }
 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }

+#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
+#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }

 #define MS { OP_MS, v_mode }
 #define XS { OP_XS, v_mode }
 #define EMCq { OP_EMC, q_mode }
 #define MS { OP_MS, v_mode }
 #define XS { OP_XS, v_mode }
 #define EMCq { OP_EMC, q_mode }


@@ -368,6 +396,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 
 #define Vex { OP_VEX, vex_mode }
 #define VexScalar { OP_VEX, vex_scalar_mode }
 
 #define Vex { OP_VEX, vex_mode }
 #define VexScalar { OP_VEX, vex_scalar_mode }

+#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }

 #define Vex128 { OP_VEX, vex128_mode }
 #define Vex256 { OP_VEX, vex256_mode }
 #define VexGdq { OP_VEX, dq_mode }
 #define Vex128 { OP_VEX, vex128_mode }
 #define Vex256 { OP_VEX, vex256_mode }
 #define VexGdq { OP_VEX, dq_mode }


@@ -389,6 +418,22 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define PCLMUL { PCLMUL_Fixup, 0 }
 #define VZERO { VZERO_Fixup, 0 }
 #define VCMP { VCMP_Fixup, 0 }
 #define PCLMUL { PCLMUL_Fixup, 0 }
 #define VZERO { VZERO_Fixup, 0 }
 #define VCMP { VCMP_Fixup, 0 }

+#define VPCMP { VPCMP_Fixup, 0 }
+
+#define EXxEVexR { OP_Rounding, evex_rounding_mode }
+#define EXxEVexS { OP_Rounding, evex_sae_mode }
+
+#define XMask { OP_Mask, mask_mode }
+#define MaskG { OP_G, mask_mode }
+#define MaskE { OP_E, mask_mode }
+#define MaskBDE { OP_E, mask_bd_mode }
+#define MaskR { OP_R, mask_mode }
+#define MaskVex { OP_VEX, mask_mode }
+
+#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
+#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
+#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
+#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }

 
 /* Used handle "rep" prefix for string instructions.  */
 #define Xbr { REP_Fixup, eSI_reg }
 
 /* Used handle "rep" prefix for string instructions.  */
 #define Xbr { REP_Fixup, eSI_reg }


@@ -400,6 +445,16 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define ALr { REP_Fixup, al_reg }
 #define eAXr { REP_Fixup, eAX_reg }
 
 #define ALr { REP_Fixup, al_reg }
 #define eAXr { REP_Fixup, eAX_reg }
 

+/* Used handle HLE prefix for lockable instructions.  */
+#define Ebh1 { HLE_Fixup1, b_mode }
+#define Evh1 { HLE_Fixup1, v_mode }
+#define Ebh2 { HLE_Fixup2, b_mode }
+#define Evh2 { HLE_Fixup2, v_mode }
+#define Ebh3 { HLE_Fixup3, b_mode }
+#define Evh3 { HLE_Fixup3, v_mode }
+
+#define BND { BND_Fixup, 0 }
+

 #define cond_jump_flag { NULL, cond_jump_mode }
 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 
 #define cond_jump_flag { NULL, cond_jump_mode }
 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 


@@ -414,6 +469,8 @@ enum
   b_mode = 1,
   /* byte operand with operand swapped */
   b_swap_mode,
   b_mode = 1,
   /* byte operand with operand swapped */
   b_swap_mode,

+  /* byte operand, sign extend like 'T' suffix */
+  b_T_mode,

   /* operand size depends on prefixes */
   v_mode,
   /* operand size depends on prefixes with operand swapped */
   /* operand size depends on prefixes */
   v_mode,
   /* operand size depends on prefixes with operand swapped */


@@ -430,26 +487,58 @@ enum
   q_swap_mode,
   /* ten-byte operand */
   t_mode,
   q_swap_mode,
   /* ten-byte operand */
   t_mode,

-  /* 16-byte XMM or 32-byte YMM operand */
+  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
+     broadcast enabled.  */

   x_mode,
   x_mode,

-  /* 16-byte XMM or 32-byte YMM operand with operand swapped */
+  /* Similar to x_mode, but with different EVEX mem shifts.  */
+  evex_x_gscat_mode,
+  /* Similar to x_mode, but with disabled broadcast.  */
+  evex_x_nobcst_mode,
+  /* Similar to x_mode, but with operands swapped and disabled broadcast
+     in EVEX.  */

   x_swap_mode,
   /* 16-byte XMM operand */
   xmm_mode,
   x_swap_mode,
   /* 16-byte XMM operand */
   xmm_mode,

-  /* 16-byte XMM or quad word operand */
+  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
+     memory operand (depending on vector length).  Broadcast isn't
+     allowed.  */

   xmmq_mode,
   xmmq_mode,

-  /* 32-byte YMM or quad word operand */
+  /* Same as xmmq_mode, but broadcast is allowed.  */
+  evex_half_bcst_xmmq_mode,
+  /* XMM register or byte memory operand */
+  xmm_mb_mode,
+  /* XMM register or word memory operand */
+  xmm_mw_mode,
+  /* XMM register or double word memory operand */
+  xmm_md_mode,
+  /* XMM register or quad word memory operand */
+  xmm_mq_mode,
+  /* XMM register or double/quad word memory operand, depending on
+     VEX.W.  */
+  xmm_mdq_mode,
+  /* 16-byte XMM, word, double word or quad word operand.  */
+  xmmdw_mode,
+  /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
+  xmmqd_mode,
+  /* 32-byte YMM operand */
+  ymm_mode,
+  /* quad word, ymmword or zmmword memory operand.  */

   ymmq_mode,
   ymmq_mode,

+  /* 32-byte YMM or 16-byte word operand */
+  ymmxmm_mode,

   /* d_mode in 32bit, q_mode in 64bit mode.  */
   m_mode,
   /* pair of v_mode operands */
   a_mode,
   cond_jump_mode,
   loop_jcxz_mode,
   /* d_mode in 32bit, q_mode in 64bit mode.  */
   m_mode,
   /* pair of v_mode operands */
   a_mode,
   cond_jump_mode,
   loop_jcxz_mode,

+  v_bnd_mode,

   /* operand size depends on REX prefixes.  */
   dq_mode,
   /* registers like dq_mode, memory like w_mode.  */
   dqw_mode,
   /* operand size depends on REX prefixes.  */
   dq_mode,
   /* registers like dq_mode, memory like w_mode.  */
   dqw_mode,

+  dqw_swap_mode,
+  bnd_mode,

   /* 4- or 6-byte pointer operand */
   f_mode,
   const_1_mode,
   /* 4- or 6-byte pointer operand */
   f_mode,
   const_1_mode,


@@ -461,6 +550,10 @@ enum
   o_mode,
   /* registers like dq_mode, memory like b_mode.  */
   dqb_mode,
   o_mode,
   /* registers like dq_mode, memory like b_mode.  */
   dqb_mode,

+  /* registers like d_mode, memory like b_mode.  */
+  db_mode,
+  /* registers like d_mode, memory like w_mode.  */
+  dw_mode,

   /* registers like dq_mode, memory like d_mode.  */
   dqd_mode,
   /* normal vex mode */
   /* registers like dq_mode, memory like d_mode.  */
   dqd_mode,
   /* normal vex mode */


@@ -472,6 +565,15 @@ enum
   /* operand size depends on the VEX.W bit.  */
   vex_w_dq_mode,
 
   /* operand size depends on the VEX.W bit.  */
   vex_w_dq_mode,
 

+  /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
+  vex_vsib_d_w_dq_mode,
+  /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
+  vex_vsib_d_w_d_mode,
+  /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
+  vex_vsib_q_w_dq_mode,
+  /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
+  vex_vsib_q_w_d_mode,
+

   /* scalar, ignore vector length.  */
   scalar_mode,
   /* like d_mode, ignore vector length.  */
   /* scalar, ignore vector length.  */
   scalar_mode,
   /* like d_mode, ignore vector length.  */


@@ -487,6 +589,16 @@ enum
   /* like vex_w_dq_mode, ignore vector length.  */
   vex_scalar_w_dq_mode,
 
   /* like vex_w_dq_mode, ignore vector length.  */
   vex_scalar_w_dq_mode,
 

+  /* Static rounding.  */
+  evex_rounding_mode,
+  /* Supress all exceptions.  */
+  evex_sae_mode,
+
+  /* Mask register operand.  */
+  mask_mode,
+  /* Mask register operand.  */
+  mask_bd_mode,
+

   es_reg,
   cs_reg,
   ss_reg,
   es_reg,
   cs_reg,
   ss_reg,


@@ -547,7 +659,8 @@ enum
   USE_VEX_C4_TABLE,
   USE_VEX_C5_TABLE,
   USE_VEX_LEN_TABLE,
   USE_VEX_C4_TABLE,
   USE_VEX_C5_TABLE,
   USE_VEX_LEN_TABLE,

-  USE_VEX_W_TABLE
+  USE_VEX_W_TABLE,
+  USE_EVEX_TABLE

 };
 
 #define FLOAT                  NULL, { { NULL, FLOATCODE } }
 };
 
 #define FLOAT                  NULL, { { NULL, FLOATCODE } }


@@ -564,6 +677,7 @@ enum
 #define VEX_C5_TABLE(I)                DIS386 (USE_VEX_C5_TABLE, (I))
 #define VEX_LEN_TABLE(I)       DIS386 (USE_VEX_LEN_TABLE, (I))
 #define VEX_W_TABLE(I)         DIS386 (USE_VEX_W_TABLE, (I))
 #define VEX_C5_TABLE(I)                DIS386 (USE_VEX_C5_TABLE, (I))
 #define VEX_LEN_TABLE(I)       DIS386 (USE_VEX_LEN_TABLE, (I))
 #define VEX_W_TABLE(I)         DIS386 (USE_VEX_W_TABLE, (I))

+#define EVEX_TABLE(I)          DIS386 (USE_EVEX_TABLE, (I))

 
 enum
 {
 
 enum
 {


@@ -603,12 +717,22 @@ enum
   REG_XOP_LWPCB,
   REG_XOP_LWP,
   REG_XOP_TBM_01,
   REG_XOP_LWPCB,
   REG_XOP_LWP,
   REG_XOP_TBM_01,

-  REG_XOP_TBM_02
+  REG_XOP_TBM_02,
+
+  REG_EVEX_0F71,
+  REG_EVEX_0F72,
+  REG_EVEX_0F73,
+  REG_EVEX_0F38C6,
+  REG_EVEX_0F38C7

 };
 
 enum
 {
   MOD_8D = 0,
 };
 
 enum
 {
   MOD_8D = 0,

+  MOD_C6_REG_7,
+  MOD_C7_REG_7,
+  MOD_FF_REG_3,
+  MOD_FF_REG_5,

   MOD_0F01_REG_0,
   MOD_0F01_REG_1,
   MOD_0F01_REG_2,
   MOD_0F01_REG_0,
   MOD_0F01_REG_1,
   MOD_0F01_REG_2,


@@ -622,10 +746,13 @@ enum
   MOD_0F18_REG_1,
   MOD_0F18_REG_2,
   MOD_0F18_REG_3,
   MOD_0F18_REG_1,
   MOD_0F18_REG_2,
   MOD_0F18_REG_3,

-  MOD_0F20,
-  MOD_0F21,
-  MOD_0F22,
-  MOD_0F23,
+  MOD_0F18_REG_4,
+  MOD_0F18_REG_5,
+  MOD_0F18_REG_6,
+  MOD_0F18_REG_7,
+  MOD_0F1A_PREFIX_0,
+  MOD_0F1B_PREFIX_0,
+  MOD_0F1B_PREFIX_1,

   MOD_0F24,
   MOD_0F26,
   MOD_0F2B_PREFIX_0,
   MOD_0F24,
   MOD_0F26,
   MOD_0F2B_PREFIX_0,


@@ -654,6 +781,9 @@ enum
   MOD_0FB2,
   MOD_0FB4,
   MOD_0FB5,
   MOD_0FB2,
   MOD_0FB4,
   MOD_0FB5,

+  MOD_0FC7_REG_3,
+  MOD_0FC7_REG_4,
+  MOD_0FC7_REG_5,

   MOD_0FC7_REG_6,
   MOD_0FC7_REG_7,
   MOD_0FD7,
   MOD_0FC7_REG_6,
   MOD_0FC7_REG_7,
   MOD_0FD7,


@@ -684,19 +814,37 @@ enum
   MOD_VEX_0FD7_PREFIX_2,
   MOD_VEX_0FE7_PREFIX_2,
   MOD_VEX_0FF0_PREFIX_3,
   MOD_VEX_0FD7_PREFIX_2,
   MOD_VEX_0FE7_PREFIX_2,
   MOD_VEX_0FF0_PREFIX_3,

-  MOD_VEX_0F3818_PREFIX_2,
-  MOD_VEX_0F3819_PREFIX_2,

   MOD_VEX_0F381A_PREFIX_2,
   MOD_VEX_0F382A_PREFIX_2,
   MOD_VEX_0F382C_PREFIX_2,
   MOD_VEX_0F382D_PREFIX_2,
   MOD_VEX_0F382E_PREFIX_2,
   MOD_VEX_0F381A_PREFIX_2,
   MOD_VEX_0F382A_PREFIX_2,
   MOD_VEX_0F382C_PREFIX_2,
   MOD_VEX_0F382D_PREFIX_2,
   MOD_VEX_0F382E_PREFIX_2,

-  MOD_VEX_0F382F_PREFIX_2
+  MOD_VEX_0F382F_PREFIX_2,
+  MOD_VEX_0F385A_PREFIX_2,
+  MOD_VEX_0F388C_PREFIX_2,
+  MOD_VEX_0F388E_PREFIX_2,
+
+  MOD_EVEX_0F10_PREFIX_1,
+  MOD_EVEX_0F10_PREFIX_3,
+  MOD_EVEX_0F11_PREFIX_1,
+  MOD_EVEX_0F11_PREFIX_3,
+  MOD_EVEX_0F12_PREFIX_0,
+  MOD_EVEX_0F16_PREFIX_0,
+  MOD_EVEX_0F38C6_REG_1,
+  MOD_EVEX_0F38C6_REG_2,
+  MOD_EVEX_0F38C6_REG_5,
+  MOD_EVEX_0F38C6_REG_6,
+  MOD_EVEX_0F38C7_REG_1,
+  MOD_EVEX_0F38C7_REG_2,
+  MOD_EVEX_0F38C7_REG_5,
+  MOD_EVEX_0F38C7_REG_6

 };
 
 enum
 {
 };
 
 enum
 {

-  RM_0F01_REG_0 = 0,
+  RM_C6_REG_7 = 0,
+  RM_C7_REG_7,
+  RM_0F01_REG_0,

   RM_0F01_REG_1,
   RM_0F01_REG_2,
   RM_0F01_REG_3,
   RM_0F01_REG_1,
   RM_0F01_REG_2,
   RM_0F01_REG_3,


@@ -713,6 +861,8 @@ enum
   PREFIX_0F11,
   PREFIX_0F12,
   PREFIX_0F16,
   PREFIX_0F11,
   PREFIX_0F12,
   PREFIX_0F16,

+  PREFIX_0F1A,
+  PREFIX_0F1B,

   PREFIX_0F2A,
   PREFIX_0F2B,
   PREFIX_0F2C,
   PREFIX_0F2A,
   PREFIX_0F2B,
   PREFIX_0F2C,


@@ -749,6 +899,9 @@ enum
   PREFIX_0FAE_REG_1,
   PREFIX_0FAE_REG_2,
   PREFIX_0FAE_REG_3,
   PREFIX_0FAE_REG_1,
   PREFIX_0FAE_REG_2,
   PREFIX_0FAE_REG_3,

+  PREFIX_0FAE_REG_6,
+  PREFIX_0FAE_REG_7,
+  PREFIX_RM_0_0FAE_REG_7,

   PREFIX_0FB8,
   PREFIX_0FBC,
   PREFIX_0FBD,
   PREFIX_0FB8,
   PREFIX_0FBC,
   PREFIX_0FBD,


@@ -794,6 +947,13 @@ enum
   PREFIX_0F3841,
   PREFIX_0F3880,
   PREFIX_0F3881,
   PREFIX_0F3841,
   PREFIX_0F3880,
   PREFIX_0F3881,

+  PREFIX_0F3882,
+  PREFIX_0F38C8,
+  PREFIX_0F38C9,
+  PREFIX_0F38CA,
+  PREFIX_0F38CB,
+  PREFIX_0F38CC,
+  PREFIX_0F38CD,

   PREFIX_0F38DB,
   PREFIX_0F38DC,
   PREFIX_0F38DD,
   PREFIX_0F38DB,
   PREFIX_0F38DC,
   PREFIX_0F38DD,


@@ -801,6 +961,7 @@ enum
   PREFIX_0F38DF,
   PREFIX_0F38F0,
   PREFIX_0F38F1,
   PREFIX_0F38DF,
   PREFIX_0F38F0,
   PREFIX_0F38F1,

+  PREFIX_0F38F6,

   PREFIX_0F3A08,
   PREFIX_0F3A09,
   PREFIX_0F3A0A,
   PREFIX_0F3A08,
   PREFIX_0F3A09,
   PREFIX_0F3A0A,


@@ -823,6 +984,7 @@ enum
   PREFIX_0F3A61,
   PREFIX_0F3A62,
   PREFIX_0F3A63,
   PREFIX_0F3A61,
   PREFIX_0F3A62,
   PREFIX_0F3A63,

+  PREFIX_0F3ACC,

   PREFIX_0F3ADF,
   PREFIX_VEX_0F10,
   PREFIX_VEX_0F11,
   PREFIX_0F3ADF,
   PREFIX_VEX_0F10,
   PREFIX_VEX_0F11,


@@ -833,6 +995,14 @@ enum
   PREFIX_VEX_0F2D,
   PREFIX_VEX_0F2E,
   PREFIX_VEX_0F2F,
   PREFIX_VEX_0F2D,
   PREFIX_VEX_0F2E,
   PREFIX_VEX_0F2F,

+  PREFIX_VEX_0F41,
+  PREFIX_VEX_0F42,
+  PREFIX_VEX_0F44,
+  PREFIX_VEX_0F45,
+  PREFIX_VEX_0F46,
+  PREFIX_VEX_0F47,
+  PREFIX_VEX_0F4A,
+  PREFIX_VEX_0F4B,

   PREFIX_VEX_0F51,
   PREFIX_VEX_0F52,
   PREFIX_VEX_0F53,
   PREFIX_VEX_0F51,
   PREFIX_VEX_0F52,
   PREFIX_VEX_0F53,


@@ -879,6 +1049,12 @@ enum
   PREFIX_VEX_0F7D,
   PREFIX_VEX_0F7E,
   PREFIX_VEX_0F7F,
   PREFIX_VEX_0F7D,
   PREFIX_VEX_0F7E,
   PREFIX_VEX_0F7F,

+  PREFIX_VEX_0F90,
+  PREFIX_VEX_0F91,
+  PREFIX_VEX_0F92,
+  PREFIX_VEX_0F93,
+  PREFIX_VEX_0F98,
+  PREFIX_VEX_0F99,

   PREFIX_VEX_0FC2,
   PREFIX_VEX_0FC4,
   PREFIX_VEX_0FC5,
   PREFIX_VEX_0FC2,
   PREFIX_VEX_0FC4,
   PREFIX_VEX_0FC5,


@@ -946,6 +1122,7 @@ enum
   PREFIX_VEX_0F380E,
   PREFIX_VEX_0F380F,
   PREFIX_VEX_0F3813,
   PREFIX_VEX_0F380E,
   PREFIX_VEX_0F380F,
   PREFIX_VEX_0F3813,

+  PREFIX_VEX_0F3816,

   PREFIX_VEX_0F3817,
   PREFIX_VEX_0F3818,
   PREFIX_VEX_0F3819,
   PREFIX_VEX_0F3817,
   PREFIX_VEX_0F3818,
   PREFIX_VEX_0F3819,


@@ -973,6 +1150,7 @@ enum
   PREFIX_VEX_0F3833,
   PREFIX_VEX_0F3834,
   PREFIX_VEX_0F3835,
   PREFIX_VEX_0F3833,
   PREFIX_VEX_0F3834,
   PREFIX_VEX_0F3835,

+  PREFIX_VEX_0F3836,

   PREFIX_VEX_0F3837,
   PREFIX_VEX_0F3838,
   PREFIX_VEX_0F3839,
   PREFIX_VEX_0F3837,
   PREFIX_VEX_0F3838,
   PREFIX_VEX_0F3839,


@@ -984,6 +1162,20 @@ enum
   PREFIX_VEX_0F383F,
   PREFIX_VEX_0F3840,
   PREFIX_VEX_0F3841,
   PREFIX_VEX_0F383F,
   PREFIX_VEX_0F3840,
   PREFIX_VEX_0F3841,

+  PREFIX_VEX_0F3845,
+  PREFIX_VEX_0F3846,
+  PREFIX_VEX_0F3847,
+  PREFIX_VEX_0F3858,
+  PREFIX_VEX_0F3859,
+  PREFIX_VEX_0F385A,
+  PREFIX_VEX_0F3878,
+  PREFIX_VEX_0F3879,
+  PREFIX_VEX_0F388C,
+  PREFIX_VEX_0F388E,
+  PREFIX_VEX_0F3890,
+  PREFIX_VEX_0F3891,
+  PREFIX_VEX_0F3892,
+  PREFIX_VEX_0F3893,

   PREFIX_VEX_0F3896,
   PREFIX_VEX_0F3897,
   PREFIX_VEX_0F3898,
   PREFIX_VEX_0F3896,
   PREFIX_VEX_0F3897,
   PREFIX_VEX_0F3898,


@@ -1023,7 +1215,12 @@ enum
   PREFIX_VEX_0F38F3_REG_1,
   PREFIX_VEX_0F38F3_REG_2,
   PREFIX_VEX_0F38F3_REG_3,
   PREFIX_VEX_0F38F3_REG_1,
   PREFIX_VEX_0F38F3_REG_2,
   PREFIX_VEX_0F38F3_REG_3,

+  PREFIX_VEX_0F38F5,
+  PREFIX_VEX_0F38F6,

   PREFIX_VEX_0F38F7,
   PREFIX_VEX_0F38F7,

+  PREFIX_VEX_0F3A00,
+  PREFIX_VEX_0F3A01,
+  PREFIX_VEX_0F3A02,

   PREFIX_VEX_0F3A04,
   PREFIX_VEX_0F3A05,
   PREFIX_VEX_0F3A06,
   PREFIX_VEX_0F3A04,
   PREFIX_VEX_0F3A05,
   PREFIX_VEX_0F3A06,


@@ -1045,10 +1242,17 @@ enum
   PREFIX_VEX_0F3A20,
   PREFIX_VEX_0F3A21,
   PREFIX_VEX_0F3A22,
   PREFIX_VEX_0F3A20,
   PREFIX_VEX_0F3A21,
   PREFIX_VEX_0F3A22,

+  PREFIX_VEX_0F3A30,
+  PREFIX_VEX_0F3A31,
+  PREFIX_VEX_0F3A32,
+  PREFIX_VEX_0F3A33,
+  PREFIX_VEX_0F3A38,
+  PREFIX_VEX_0F3A39,

   PREFIX_VEX_0F3A40,
   PREFIX_VEX_0F3A41,
   PREFIX_VEX_0F3A42,
   PREFIX_VEX_0F3A44,
   PREFIX_VEX_0F3A40,
   PREFIX_VEX_0F3A41,
   PREFIX_VEX_0F3A42,
   PREFIX_VEX_0F3A44,

+  PREFIX_VEX_0F3A46,

   PREFIX_VEX_0F3A48,
   PREFIX_VEX_0F3A49,
   PREFIX_VEX_0F3A4A,
   PREFIX_VEX_0F3A48,
   PREFIX_VEX_0F3A49,
   PREFIX_VEX_0F3A4A,


@@ -1078,7 +1282,307 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,

-  PREFIX_VEX_0F3ADF
+  PREFIX_VEX_0F3ADF,
+  PREFIX_VEX_0F3AF0,
+
+  PREFIX_EVEX_0F10,
+  PREFIX_EVEX_0F11,
+  PREFIX_EVEX_0F12,
+  PREFIX_EVEX_0F13,
+  PREFIX_EVEX_0F14,
+  PREFIX_EVEX_0F15,
+  PREFIX_EVEX_0F16,
+  PREFIX_EVEX_0F17,
+  PREFIX_EVEX_0F28,
+  PREFIX_EVEX_0F29,
+  PREFIX_EVEX_0F2A,
+  PREFIX_EVEX_0F2B,
+  PREFIX_EVEX_0F2C,
+  PREFIX_EVEX_0F2D,
+  PREFIX_EVEX_0F2E,
+  PREFIX_EVEX_0F2F,
+  PREFIX_EVEX_0F51,
+  PREFIX_EVEX_0F54,
+  PREFIX_EVEX_0F55,
+  PREFIX_EVEX_0F56,
+  PREFIX_EVEX_0F57,
+  PREFIX_EVEX_0F58,
+  PREFIX_EVEX_0F59,
+  PREFIX_EVEX_0F5A,
+  PREFIX_EVEX_0F5B,
+  PREFIX_EVEX_0F5C,
+  PREFIX_EVEX_0F5D,
+  PREFIX_EVEX_0F5E,
+  PREFIX_EVEX_0F5F,
+  PREFIX_EVEX_0F60,
+  PREFIX_EVEX_0F61,
+  PREFIX_EVEX_0F62,
+  PREFIX_EVEX_0F63,
+  PREFIX_EVEX_0F64,
+  PREFIX_EVEX_0F65,
+  PREFIX_EVEX_0F66,
+  PREFIX_EVEX_0F67,
+  PREFIX_EVEX_0F68,
+  PREFIX_EVEX_0F69,
+  PREFIX_EVEX_0F6A,
+  PREFIX_EVEX_0F6B,
+  PREFIX_EVEX_0F6C,
+  PREFIX_EVEX_0F6D,
+  PREFIX_EVEX_0F6E,
+  PREFIX_EVEX_0F6F,
+  PREFIX_EVEX_0F70,
+  PREFIX_EVEX_0F71_REG_2,
+  PREFIX_EVEX_0F71_REG_4,
+  PREFIX_EVEX_0F71_REG_6,
+  PREFIX_EVEX_0F72_REG_0,
+  PREFIX_EVEX_0F72_REG_1,
+  PREFIX_EVEX_0F72_REG_2,
+  PREFIX_EVEX_0F72_REG_4,
+  PREFIX_EVEX_0F72_REG_6,
+  PREFIX_EVEX_0F73_REG_2,
+  PREFIX_EVEX_0F73_REG_3,
+  PREFIX_EVEX_0F73_REG_6,
+  PREFIX_EVEX_0F73_REG_7,
+  PREFIX_EVEX_0F74,
+  PREFIX_EVEX_0F75,
+  PREFIX_EVEX_0F76,
+  PREFIX_EVEX_0F78,
+  PREFIX_EVEX_0F79,
+  PREFIX_EVEX_0F7A,
+  PREFIX_EVEX_0F7B,
+  PREFIX_EVEX_0F7E,
+  PREFIX_EVEX_0F7F,
+  PREFIX_EVEX_0FC2,
+  PREFIX_EVEX_0FC4,
+  PREFIX_EVEX_0FC5,
+  PREFIX_EVEX_0FC6,
+  PREFIX_EVEX_0FD1,
+  PREFIX_EVEX_0FD2,
+  PREFIX_EVEX_0FD3,
+  PREFIX_EVEX_0FD4,
+  PREFIX_EVEX_0FD5,
+  PREFIX_EVEX_0FD6,
+  PREFIX_EVEX_0FD8,
+  PREFIX_EVEX_0FD9,
+  PREFIX_EVEX_0FDA,
+  PREFIX_EVEX_0FDB,
+  PREFIX_EVEX_0FDC,
+  PREFIX_EVEX_0FDD,
+  PREFIX_EVEX_0FDE,
+  PREFIX_EVEX_0FDF,
+  PREFIX_EVEX_0FE0,
+  PREFIX_EVEX_0FE1,
+  PREFIX_EVEX_0FE2,
+  PREFIX_EVEX_0FE3,
+  PREFIX_EVEX_0FE4,
+  PREFIX_EVEX_0FE5,
+  PREFIX_EVEX_0FE6,
+  PREFIX_EVEX_0FE7,
+  PREFIX_EVEX_0FE8,
+  PREFIX_EVEX_0FE9,
+  PREFIX_EVEX_0FEA,
+  PREFIX_EVEX_0FEB,
+  PREFIX_EVEX_0FEC,
+  PREFIX_EVEX_0FED,
+  PREFIX_EVEX_0FEE,
+  PREFIX_EVEX_0FEF,
+  PREFIX_EVEX_0FF1,
+  PREFIX_EVEX_0FF2,
+  PREFIX_EVEX_0FF3,
+  PREFIX_EVEX_0FF4,
+  PREFIX_EVEX_0FF5,
+  PREFIX_EVEX_0FF6,
+  PREFIX_EVEX_0FF8,
+  PREFIX_EVEX_0FF9,
+  PREFIX_EVEX_0FFA,
+  PREFIX_EVEX_0FFB,
+  PREFIX_EVEX_0FFC,
+  PREFIX_EVEX_0FFD,
+  PREFIX_EVEX_0FFE,
+  PREFIX_EVEX_0F3800,
+  PREFIX_EVEX_0F3804,
+  PREFIX_EVEX_0F380B,
+  PREFIX_EVEX_0F380C,
+  PREFIX_EVEX_0F380D,
+  PREFIX_EVEX_0F3810,
+  PREFIX_EVEX_0F3811,
+  PREFIX_EVEX_0F3812,
+  PREFIX_EVEX_0F3813,
+  PREFIX_EVEX_0F3814,
+  PREFIX_EVEX_0F3815,
+  PREFIX_EVEX_0F3816,
+  PREFIX_EVEX_0F3818,
+  PREFIX_EVEX_0F3819,
+  PREFIX_EVEX_0F381A,
+  PREFIX_EVEX_0F381B,
+  PREFIX_EVEX_0F381C,
+  PREFIX_EVEX_0F381D,
+  PREFIX_EVEX_0F381E,
+  PREFIX_EVEX_0F381F,
+  PREFIX_EVEX_0F3820,
+  PREFIX_EVEX_0F3821,
+  PREFIX_EVEX_0F3822,
+  PREFIX_EVEX_0F3823,
+  PREFIX_EVEX_0F3824,
+  PREFIX_EVEX_0F3825,
+  PREFIX_EVEX_0F3826,
+  PREFIX_EVEX_0F3827,
+  PREFIX_EVEX_0F3828,
+  PREFIX_EVEX_0F3829,
+  PREFIX_EVEX_0F382A,
+  PREFIX_EVEX_0F382B,
+  PREFIX_EVEX_0F382C,
+  PREFIX_EVEX_0F382D,
+  PREFIX_EVEX_0F3830,
+  PREFIX_EVEX_0F3831,
+  PREFIX_EVEX_0F3832,
+  PREFIX_EVEX_0F3833,
+  PREFIX_EVEX_0F3834,
+  PREFIX_EVEX_0F3835,
+  PREFIX_EVEX_0F3836,
+  PREFIX_EVEX_0F3837,
+  PREFIX_EVEX_0F3838,
+  PREFIX_EVEX_0F3839,
+  PREFIX_EVEX_0F383A,
+  PREFIX_EVEX_0F383B,
+  PREFIX_EVEX_0F383C,
+  PREFIX_EVEX_0F383D,
+  PREFIX_EVEX_0F383E,
+  PREFIX_EVEX_0F383F,
+  PREFIX_EVEX_0F3840,
+  PREFIX_EVEX_0F3842,
+  PREFIX_EVEX_0F3843,
+  PREFIX_EVEX_0F3844,
+  PREFIX_EVEX_0F3845,
+  PREFIX_EVEX_0F3846,
+  PREFIX_EVEX_0F3847,
+  PREFIX_EVEX_0F384C,
+  PREFIX_EVEX_0F384D,
+  PREFIX_EVEX_0F384E,
+  PREFIX_EVEX_0F384F,
+  PREFIX_EVEX_0F3858,
+  PREFIX_EVEX_0F3859,
+  PREFIX_EVEX_0F385A,
+  PREFIX_EVEX_0F385B,
+  PREFIX_EVEX_0F3864,
+  PREFIX_EVEX_0F3865,
+  PREFIX_EVEX_0F3866,
+  PREFIX_EVEX_0F3875,
+  PREFIX_EVEX_0F3876,
+  PREFIX_EVEX_0F3877,
+  PREFIX_EVEX_0F3878,
+  PREFIX_EVEX_0F3879,
+  PREFIX_EVEX_0F387A,
+  PREFIX_EVEX_0F387B,
+  PREFIX_EVEX_0F387C,
+  PREFIX_EVEX_0F387D,
+  PREFIX_EVEX_0F387E,
+  PREFIX_EVEX_0F387F,
+  PREFIX_EVEX_0F3883,
+  PREFIX_EVEX_0F3888,
+  PREFIX_EVEX_0F3889,
+  PREFIX_EVEX_0F388A,
+  PREFIX_EVEX_0F388B,
+  PREFIX_EVEX_0F388D,
+  PREFIX_EVEX_0F3890,
+  PREFIX_EVEX_0F3891,
+  PREFIX_EVEX_0F3892,
+  PREFIX_EVEX_0F3893,
+  PREFIX_EVEX_0F3896,
+  PREFIX_EVEX_0F3897,
+  PREFIX_EVEX_0F3898,
+  PREFIX_EVEX_0F3899,
+  PREFIX_EVEX_0F389A,
+  PREFIX_EVEX_0F389B,
+  PREFIX_EVEX_0F389C,
+  PREFIX_EVEX_0F389D,
+  PREFIX_EVEX_0F389E,
+  PREFIX_EVEX_0F389F,
+  PREFIX_EVEX_0F38A0,
+  PREFIX_EVEX_0F38A1,
+  PREFIX_EVEX_0F38A2,
+  PREFIX_EVEX_0F38A3,
+  PREFIX_EVEX_0F38A6,
+  PREFIX_EVEX_0F38A7,
+  PREFIX_EVEX_0F38A8,
+  PREFIX_EVEX_0F38A9,
+  PREFIX_EVEX_0F38AA,
+  PREFIX_EVEX_0F38AB,
+  PREFIX_EVEX_0F38AC,
+  PREFIX_EVEX_0F38AD,
+  PREFIX_EVEX_0F38AE,
+  PREFIX_EVEX_0F38AF,
+  PREFIX_EVEX_0F38B4,
+  PREFIX_EVEX_0F38B5,
+  PREFIX_EVEX_0F38B6,
+  PREFIX_EVEX_0F38B7,
+  PREFIX_EVEX_0F38B8,
+  PREFIX_EVEX_0F38B9,
+  PREFIX_EVEX_0F38BA,
+  PREFIX_EVEX_0F38BB,
+  PREFIX_EVEX_0F38BC,
+  PREFIX_EVEX_0F38BD,
+  PREFIX_EVEX_0F38BE,
+  PREFIX_EVEX_0F38BF,
+  PREFIX_EVEX_0F38C4,
+  PREFIX_EVEX_0F38C6_REG_1,
+  PREFIX_EVEX_0F38C6_REG_2,
+  PREFIX_EVEX_0F38C6_REG_5,
+  PREFIX_EVEX_0F38C6_REG_6,
+  PREFIX_EVEX_0F38C7_REG_1,
+  PREFIX_EVEX_0F38C7_REG_2,
+  PREFIX_EVEX_0F38C7_REG_5,
+  PREFIX_EVEX_0F38C7_REG_6,
+  PREFIX_EVEX_0F38C8,
+  PREFIX_EVEX_0F38CA,
+  PREFIX_EVEX_0F38CB,
+  PREFIX_EVEX_0F38CC,
+  PREFIX_EVEX_0F38CD,
+
+  PREFIX_EVEX_0F3A00,
+  PREFIX_EVEX_0F3A01,
+  PREFIX_EVEX_0F3A03,
+  PREFIX_EVEX_0F3A04,
+  PREFIX_EVEX_0F3A05,
+  PREFIX_EVEX_0F3A08,
+  PREFIX_EVEX_0F3A09,
+  PREFIX_EVEX_0F3A0A,
+  PREFIX_EVEX_0F3A0B,
+  PREFIX_EVEX_0F3A0F,
+  PREFIX_EVEX_0F3A14,
+  PREFIX_EVEX_0F3A15,
+  PREFIX_EVEX_0F3A16,
+  PREFIX_EVEX_0F3A17,
+  PREFIX_EVEX_0F3A18,
+  PREFIX_EVEX_0F3A19,
+  PREFIX_EVEX_0F3A1A,
+  PREFIX_EVEX_0F3A1B,
+  PREFIX_EVEX_0F3A1D,
+  PREFIX_EVEX_0F3A1E,
+  PREFIX_EVEX_0F3A1F,
+  PREFIX_EVEX_0F3A20,
+  PREFIX_EVEX_0F3A21,
+  PREFIX_EVEX_0F3A22,
+  PREFIX_EVEX_0F3A23,
+  PREFIX_EVEX_0F3A25,
+  PREFIX_EVEX_0F3A26,
+  PREFIX_EVEX_0F3A27,
+  PREFIX_EVEX_0F3A38,
+  PREFIX_EVEX_0F3A39,
+  PREFIX_EVEX_0F3A3A,
+  PREFIX_EVEX_0F3A3B,
+  PREFIX_EVEX_0F3A3E,
+  PREFIX_EVEX_0F3A3F,
+  PREFIX_EVEX_0F3A42,
+  PREFIX_EVEX_0F3A43,
+  PREFIX_EVEX_0F3A50,
+  PREFIX_EVEX_0F3A51,
+  PREFIX_EVEX_0F3A54,
+  PREFIX_EVEX_0F3A55,
+  PREFIX_EVEX_0F3A56,
+  PREFIX_EVEX_0F3A57,
+  PREFIX_EVEX_0F3A66,
+  PREFIX_EVEX_0F3A67

 };
 
 enum
 };
 
 enum


@@ -1136,6 +1640,13 @@ enum
 
 enum
 {
 
 enum
 {

+  EVEX_0F = 0,
+  EVEX_0F38,
+  EVEX_0F3A
+};
+
+enum
+{

   VEX_LEN_0F10_P_1 = 0,
   VEX_LEN_0F10_P_3,
   VEX_LEN_0F11_P_1,
   VEX_LEN_0F10_P_1 = 0,
   VEX_LEN_0F10_P_3,
   VEX_LEN_0F11_P_1,


@@ -1158,6 +1669,22 @@ enum
   VEX_LEN_0F2E_P_2,
   VEX_LEN_0F2F_P_0,
   VEX_LEN_0F2F_P_2,
   VEX_LEN_0F2E_P_2,
   VEX_LEN_0F2F_P_0,
   VEX_LEN_0F2F_P_2,

+  VEX_LEN_0F41_P_0,
+  VEX_LEN_0F41_P_2,
+  VEX_LEN_0F42_P_0,
+  VEX_LEN_0F42_P_2,
+  VEX_LEN_0F44_P_0,
+  VEX_LEN_0F44_P_2,
+  VEX_LEN_0F45_P_0,
+  VEX_LEN_0F45_P_2,
+  VEX_LEN_0F46_P_0,
+  VEX_LEN_0F46_P_2,
+  VEX_LEN_0F47_P_0,
+  VEX_LEN_0F47_P_2,
+  VEX_LEN_0F4A_P_0,
+  VEX_LEN_0F4A_P_2,
+  VEX_LEN_0F4B_P_0,
+  VEX_LEN_0F4B_P_2,

   VEX_LEN_0F51_P_1,
   VEX_LEN_0F51_P_3,
   VEX_LEN_0F52_P_1,
   VEX_LEN_0F51_P_1,
   VEX_LEN_0F51_P_3,
   VEX_LEN_0F52_P_1,


@@ -1176,132 +1703,37 @@ enum
   VEX_LEN_0F5E_P_3,
   VEX_LEN_0F5F_P_1,
   VEX_LEN_0F5F_P_3,
   VEX_LEN_0F5E_P_3,
   VEX_LEN_0F5F_P_1,
   VEX_LEN_0F5F_P_3,

-  VEX_LEN_0F60_P_2,
-  VEX_LEN_0F61_P_2,
-  VEX_LEN_0F62_P_2,
-  VEX_LEN_0F63_P_2,
-  VEX_LEN_0F64_P_2,
-  VEX_LEN_0F65_P_2,
-  VEX_LEN_0F66_P_2,
-  VEX_LEN_0F67_P_2,
-  VEX_LEN_0F68_P_2,
-  VEX_LEN_0F69_P_2,
-  VEX_LEN_0F6A_P_2,
-  VEX_LEN_0F6B_P_2,
-  VEX_LEN_0F6C_P_2,
-  VEX_LEN_0F6D_P_2,

   VEX_LEN_0F6E_P_2,
   VEX_LEN_0F6E_P_2,

-  VEX_LEN_0F70_P_1,
-  VEX_LEN_0F70_P_2,
-  VEX_LEN_0F70_P_3,
-  VEX_LEN_0F71_R_2_P_2,
-  VEX_LEN_0F71_R_4_P_2,
-  VEX_LEN_0F71_R_6_P_2,
-  VEX_LEN_0F72_R_2_P_2,
-  VEX_LEN_0F72_R_4_P_2,
-  VEX_LEN_0F72_R_6_P_2,
-  VEX_LEN_0F73_R_2_P_2,
-  VEX_LEN_0F73_R_3_P_2,
-  VEX_LEN_0F73_R_6_P_2,
-  VEX_LEN_0F73_R_7_P_2,
-  VEX_LEN_0F74_P_2,
-  VEX_LEN_0F75_P_2,
-  VEX_LEN_0F76_P_2,

   VEX_LEN_0F7E_P_1,
   VEX_LEN_0F7E_P_2,
   VEX_LEN_0F7E_P_1,
   VEX_LEN_0F7E_P_2,

+  VEX_LEN_0F90_P_0,
+  VEX_LEN_0F90_P_2,
+  VEX_LEN_0F91_P_0,
+  VEX_LEN_0F91_P_2,
+  VEX_LEN_0F92_P_0,
+  VEX_LEN_0F92_P_2,
+  VEX_LEN_0F92_P_3,
+  VEX_LEN_0F93_P_0,
+  VEX_LEN_0F93_P_2,
+  VEX_LEN_0F93_P_3,
+  VEX_LEN_0F98_P_0,
+  VEX_LEN_0F98_P_2,
+  VEX_LEN_0F99_P_0,
+  VEX_LEN_0F99_P_2,

   VEX_LEN_0FAE_R_2_M_0,
   VEX_LEN_0FAE_R_3_M_0,
   VEX_LEN_0FC2_P_1,
   VEX_LEN_0FC2_P_3,
   VEX_LEN_0FC4_P_2,
   VEX_LEN_0FC5_P_2,
   VEX_LEN_0FAE_R_2_M_0,
   VEX_LEN_0FAE_R_3_M_0,
   VEX_LEN_0FC2_P_1,
   VEX_LEN_0FC2_P_3,
   VEX_LEN_0FC4_P_2,
   VEX_LEN_0FC5_P_2,

-  VEX_LEN_0FD1_P_2,
-  VEX_LEN_0FD2_P_2,
-  VEX_LEN_0FD3_P_2,
-  VEX_LEN_0FD4_P_2,
-  VEX_LEN_0FD5_P_2,

   VEX_LEN_0FD6_P_2,
   VEX_LEN_0FD6_P_2,

-  VEX_LEN_0FD7_P_2_M_1,
-  VEX_LEN_0FD8_P_2,
-  VEX_LEN_0FD9_P_2,
-  VEX_LEN_0FDA_P_2,
-  VEX_LEN_0FDB_P_2,
-  VEX_LEN_0FDC_P_2,
-  VEX_LEN_0FDD_P_2,
-  VEX_LEN_0FDE_P_2,
-  VEX_LEN_0FDF_P_2,
-  VEX_LEN_0FE0_P_2,
-  VEX_LEN_0FE1_P_2,
-  VEX_LEN_0FE2_P_2,
-  VEX_LEN_0FE3_P_2,
-  VEX_LEN_0FE4_P_2,
-  VEX_LEN_0FE5_P_2,
-  VEX_LEN_0FE8_P_2,
-  VEX_LEN_0FE9_P_2,
-  VEX_LEN_0FEA_P_2,
-  VEX_LEN_0FEB_P_2,
-  VEX_LEN_0FEC_P_2,
-  VEX_LEN_0FED_P_2,
-  VEX_LEN_0FEE_P_2,
-  VEX_LEN_0FEF_P_2,
-  VEX_LEN_0FF1_P_2,
-  VEX_LEN_0FF2_P_2,
-  VEX_LEN_0FF3_P_2,
-  VEX_LEN_0FF4_P_2,
-  VEX_LEN_0FF5_P_2,
-  VEX_LEN_0FF6_P_2,

   VEX_LEN_0FF7_P_2,
   VEX_LEN_0FF7_P_2,

-  VEX_LEN_0FF8_P_2,
-  VEX_LEN_0FF9_P_2,
-  VEX_LEN_0FFA_P_2,
-  VEX_LEN_0FFB_P_2,
-  VEX_LEN_0FFC_P_2,
-  VEX_LEN_0FFD_P_2,
-  VEX_LEN_0FFE_P_2,
-  VEX_LEN_0F3800_P_2,
-  VEX_LEN_0F3801_P_2,
-  VEX_LEN_0F3802_P_2,
-  VEX_LEN_0F3803_P_2,
-  VEX_LEN_0F3804_P_2,
-  VEX_LEN_0F3805_P_2,
-  VEX_LEN_0F3806_P_2,
-  VEX_LEN_0F3807_P_2,
-  VEX_LEN_0F3808_P_2,
-  VEX_LEN_0F3809_P_2,
-  VEX_LEN_0F380A_P_2,
-  VEX_LEN_0F380B_P_2,
-  VEX_LEN_0F3819_P_2_M_0,
+  VEX_LEN_0F3816_P_2,
+  VEX_LEN_0F3819_P_2,

   VEX_LEN_0F381A_P_2_M_0,
   VEX_LEN_0F381A_P_2_M_0,

-  VEX_LEN_0F381C_P_2,
-  VEX_LEN_0F381D_P_2,
-  VEX_LEN_0F381E_P_2,
-  VEX_LEN_0F3820_P_2,
-  VEX_LEN_0F3821_P_2,
-  VEX_LEN_0F3822_P_2,
-  VEX_LEN_0F3823_P_2,
-  VEX_LEN_0F3824_P_2,
-  VEX_LEN_0F3825_P_2,
-  VEX_LEN_0F3828_P_2,
-  VEX_LEN_0F3829_P_2,
-  VEX_LEN_0F382A_P_2_M_0,
-  VEX_LEN_0F382B_P_2,
-  VEX_LEN_0F3830_P_2,
-  VEX_LEN_0F3831_P_2,
-  VEX_LEN_0F3832_P_2,
-  VEX_LEN_0F3833_P_2,
-  VEX_LEN_0F3834_P_2,
-  VEX_LEN_0F3835_P_2,
-  VEX_LEN_0F3837_P_2,
-  VEX_LEN_0F3838_P_2,
-  VEX_LEN_0F3839_P_2,
-  VEX_LEN_0F383A_P_2,
-  VEX_LEN_0F383B_P_2,
-  VEX_LEN_0F383C_P_2,
-  VEX_LEN_0F383D_P_2,
-  VEX_LEN_0F383E_P_2,
-  VEX_LEN_0F383F_P_2,
-  VEX_LEN_0F3840_P_2,
+  VEX_LEN_0F3836_P_2,

   VEX_LEN_0F3841_P_2,
   VEX_LEN_0F3841_P_2,

+  VEX_LEN_0F385A_P_2_M_0,

   VEX_LEN_0F38DB_P_2,
   VEX_LEN_0F38DC_P_2,
   VEX_LEN_0F38DD_P_2,
   VEX_LEN_0F38DB_P_2,
   VEX_LEN_0F38DC_P_2,
   VEX_LEN_0F38DD_P_2,


@@ -1311,12 +1743,19 @@ enum
   VEX_LEN_0F38F3_R_1_P_0,
   VEX_LEN_0F38F3_R_2_P_0,
   VEX_LEN_0F38F3_R_3_P_0,
   VEX_LEN_0F38F3_R_1_P_0,
   VEX_LEN_0F38F3_R_2_P_0,
   VEX_LEN_0F38F3_R_3_P_0,

+  VEX_LEN_0F38F5_P_0,
+  VEX_LEN_0F38F5_P_1,
+  VEX_LEN_0F38F5_P_3,
+  VEX_LEN_0F38F6_P_3,

   VEX_LEN_0F38F7_P_0,
   VEX_LEN_0F38F7_P_0,

+  VEX_LEN_0F38F7_P_1,
+  VEX_LEN_0F38F7_P_2,
+  VEX_LEN_0F38F7_P_3,
+  VEX_LEN_0F3A00_P_2,
+  VEX_LEN_0F3A01_P_2,

   VEX_LEN_0F3A06_P_2,
   VEX_LEN_0F3A0A_P_2,
   VEX_LEN_0F3A0B_P_2,
   VEX_LEN_0F3A06_P_2,
   VEX_LEN_0F3A0A_P_2,
   VEX_LEN_0F3A0B_P_2,

-  VEX_LEN_0F3A0E_P_2,
-  VEX_LEN_0F3A0F_P_2,

   VEX_LEN_0F3A14_P_2,
   VEX_LEN_0F3A15_P_2,
   VEX_LEN_0F3A16_P_2,
   VEX_LEN_0F3A14_P_2,
   VEX_LEN_0F3A15_P_2,
   VEX_LEN_0F3A16_P_2,


@@ -1326,10 +1765,15 @@ enum
   VEX_LEN_0F3A20_P_2,
   VEX_LEN_0F3A21_P_2,
   VEX_LEN_0F3A22_P_2,
   VEX_LEN_0F3A20_P_2,
   VEX_LEN_0F3A21_P_2,
   VEX_LEN_0F3A22_P_2,

+  VEX_LEN_0F3A30_P_2,
+  VEX_LEN_0F3A31_P_2,
+  VEX_LEN_0F3A32_P_2,
+  VEX_LEN_0F3A33_P_2,
+  VEX_LEN_0F3A38_P_2,
+  VEX_LEN_0F3A39_P_2,

   VEX_LEN_0F3A41_P_2,
   VEX_LEN_0F3A41_P_2,

-  VEX_LEN_0F3A42_P_2,

   VEX_LEN_0F3A44_P_2,
   VEX_LEN_0F3A44_P_2,

-  VEX_LEN_0F3A4C_P_2,
+  VEX_LEN_0F3A46_P_2,

   VEX_LEN_0F3A60_P_2,
   VEX_LEN_0F3A61_P_2,
   VEX_LEN_0F3A62_P_2,
   VEX_LEN_0F3A60_P_2,
   VEX_LEN_0F3A61_P_2,
   VEX_LEN_0F3A62_P_2,


@@ -1343,6 +1787,15 @@ enum
   VEX_LEN_0F3A7E_P_2,
   VEX_LEN_0F3A7F_P_2,
   VEX_LEN_0F3ADF_P_2,
   VEX_LEN_0F3A7E_P_2,
   VEX_LEN_0F3A7F_P_2,
   VEX_LEN_0F3ADF_P_2,

+  VEX_LEN_0F3AF0_P_3,
+  VEX_LEN_0FXOP_08_CC,
+  VEX_LEN_0FXOP_08_CD,
+  VEX_LEN_0FXOP_08_CE,
+  VEX_LEN_0FXOP_08_CF,
+  VEX_LEN_0FXOP_08_EC,
+  VEX_LEN_0FXOP_08_ED,
+  VEX_LEN_0FXOP_08_EE,
+  VEX_LEN_0FXOP_08_EF,

   VEX_LEN_0FXOP_09_80,
   VEX_LEN_0FXOP_09_81
 };
   VEX_LEN_0FXOP_09_80,
   VEX_LEN_0FXOP_09_81
 };


@@ -1377,6 +1830,22 @@ enum
   VEX_W_0F2E_P_2,
   VEX_W_0F2F_P_0,
   VEX_W_0F2F_P_2,
   VEX_W_0F2E_P_2,
   VEX_W_0F2F_P_0,
   VEX_W_0F2F_P_2,

+  VEX_W_0F41_P_0_LEN_1,
+  VEX_W_0F41_P_2_LEN_1,
+  VEX_W_0F42_P_0_LEN_1,
+  VEX_W_0F42_P_2_LEN_1,
+  VEX_W_0F44_P_0_LEN_0,
+  VEX_W_0F44_P_2_LEN_0,
+  VEX_W_0F45_P_0_LEN_1,
+  VEX_W_0F45_P_2_LEN_1,
+  VEX_W_0F46_P_0_LEN_1,
+  VEX_W_0F46_P_2_LEN_1,
+  VEX_W_0F47_P_0_LEN_1,
+  VEX_W_0F47_P_2_LEN_1,
+  VEX_W_0F4A_P_0_LEN_1,
+  VEX_W_0F4A_P_2_LEN_1,
+  VEX_W_0F4B_P_0_LEN_1,
+  VEX_W_0F4B_P_2_LEN_1,

   VEX_W_0F50_M_0,
   VEX_W_0F51_P_0,
   VEX_W_0F51_P_1,
   VEX_W_0F50_M_0,
   VEX_W_0F51_P_0,
   VEX_W_0F51_P_1,


@@ -1456,6 +1925,20 @@ enum
   VEX_W_0F7E_P_1,
   VEX_W_0F7F_P_1,
   VEX_W_0F7F_P_2,
   VEX_W_0F7E_P_1,
   VEX_W_0F7F_P_1,
   VEX_W_0F7F_P_2,

+  VEX_W_0F90_P_0_LEN_0,
+  VEX_W_0F90_P_2_LEN_0,
+  VEX_W_0F91_P_0_LEN_0,
+  VEX_W_0F91_P_2_LEN_0,
+  VEX_W_0F92_P_0_LEN_0,
+  VEX_W_0F92_P_2_LEN_0,
+  VEX_W_0F92_P_3_LEN_0,
+  VEX_W_0F93_P_0_LEN_0,
+  VEX_W_0F93_P_2_LEN_0,
+  VEX_W_0F93_P_3_LEN_0,
+  VEX_W_0F98_P_0_LEN_0,
+  VEX_W_0F98_P_2_LEN_0,
+  VEX_W_0F99_P_0_LEN_0,
+  VEX_W_0F99_P_2_LEN_0,

   VEX_W_0FAE_R_2_M_0,
   VEX_W_0FAE_R_3_M_0,
   VEX_W_0FC2_P_0,
   VEX_W_0FAE_R_2_M_0,
   VEX_W_0FAE_R_3_M_0,
   VEX_W_0FC2_P_0,


@@ -1530,9 +2013,10 @@ enum
   VEX_W_0F380D_P_2,
   VEX_W_0F380E_P_2,
   VEX_W_0F380F_P_2,
   VEX_W_0F380D_P_2,
   VEX_W_0F380E_P_2,
   VEX_W_0F380F_P_2,

+  VEX_W_0F3816_P_2,

   VEX_W_0F3817_P_2,
   VEX_W_0F3817_P_2,

-  VEX_W_0F3818_P_2_M_0,
-  VEX_W_0F3819_P_2_M_0,
+  VEX_W_0F3818_P_2,
+  VEX_W_0F3819_P_2,

   VEX_W_0F381A_P_2_M_0,
   VEX_W_0F381C_P_2,
   VEX_W_0F381D_P_2,
   VEX_W_0F381A_P_2_M_0,
   VEX_W_0F381C_P_2,
   VEX_W_0F381D_P_2,


@@ -1557,6 +2041,7 @@ enum
   VEX_W_0F3833_P_2,
   VEX_W_0F3834_P_2,
   VEX_W_0F3835_P_2,
   VEX_W_0F3833_P_2,
   VEX_W_0F3834_P_2,
   VEX_W_0F3835_P_2,

+  VEX_W_0F3836_P_2,

   VEX_W_0F3837_P_2,
   VEX_W_0F3838_P_2,
   VEX_W_0F3839_P_2,
   VEX_W_0F3837_P_2,
   VEX_W_0F3838_P_2,
   VEX_W_0F3839_P_2,


@@ -1568,11 +2053,20 @@ enum
   VEX_W_0F383F_P_2,
   VEX_W_0F3840_P_2,
   VEX_W_0F3841_P_2,
   VEX_W_0F383F_P_2,
   VEX_W_0F3840_P_2,
   VEX_W_0F3841_P_2,

+  VEX_W_0F3846_P_2,
+  VEX_W_0F3858_P_2,
+  VEX_W_0F3859_P_2,
+  VEX_W_0F385A_P_2_M_0,
+  VEX_W_0F3878_P_2,
+  VEX_W_0F3879_P_2,

   VEX_W_0F38DB_P_2,
   VEX_W_0F38DC_P_2,
   VEX_W_0F38DD_P_2,
   VEX_W_0F38DE_P_2,
   VEX_W_0F38DF_P_2,
   VEX_W_0F38DB_P_2,
   VEX_W_0F38DC_P_2,
   VEX_W_0F38DD_P_2,
   VEX_W_0F38DE_P_2,
   VEX_W_0F38DF_P_2,

+  VEX_W_0F3A00_P_2,
+  VEX_W_0F3A01_P_2,
+  VEX_W_0F3A02_P_2,

   VEX_W_0F3A04_P_2,
   VEX_W_0F3A05_P_2,
   VEX_W_0F3A06_P_2,
   VEX_W_0F3A04_P_2,
   VEX_W_0F3A05_P_2,
   VEX_W_0F3A06_P_2,


@@ -1590,10 +2084,17 @@ enum
   VEX_W_0F3A19_P_2,
   VEX_W_0F3A20_P_2,
   VEX_W_0F3A21_P_2,
   VEX_W_0F3A19_P_2,
   VEX_W_0F3A20_P_2,
   VEX_W_0F3A21_P_2,

+  VEX_W_0F3A30_P_2_LEN_0,
+  VEX_W_0F3A31_P_2_LEN_0,
+  VEX_W_0F3A32_P_2_LEN_0,
+  VEX_W_0F3A33_P_2_LEN_0,
+  VEX_W_0F3A38_P_2,
+  VEX_W_0F3A39_P_2,

   VEX_W_0F3A40_P_2,
   VEX_W_0F3A41_P_2,
   VEX_W_0F3A42_P_2,
   VEX_W_0F3A44_P_2,
   VEX_W_0F3A40_P_2,
   VEX_W_0F3A41_P_2,
   VEX_W_0F3A42_P_2,
   VEX_W_0F3A44_P_2,

+  VEX_W_0F3A46_P_2,

   VEX_W_0F3A48_P_2,
   VEX_W_0F3A49_P_2,
   VEX_W_0F3A4A_P_2,
   VEX_W_0F3A48_P_2,
   VEX_W_0F3A49_P_2,
   VEX_W_0F3A4A_P_2,


@@ -1603,7 +2104,242 @@ enum
   VEX_W_0F3A61_P_2,
   VEX_W_0F3A62_P_2,
   VEX_W_0F3A63_P_2,
   VEX_W_0F3A61_P_2,
   VEX_W_0F3A62_P_2,
   VEX_W_0F3A63_P_2,

-  VEX_W_0F3ADF_P_2
+  VEX_W_0F3ADF_P_2,
+
+  EVEX_W_0F10_P_0,
+  EVEX_W_0F10_P_1_M_0,
+  EVEX_W_0F10_P_1_M_1,
+  EVEX_W_0F10_P_2,
+  EVEX_W_0F10_P_3_M_0,
+  EVEX_W_0F10_P_3_M_1,
+  EVEX_W_0F11_P_0,
+  EVEX_W_0F11_P_1_M_0,
+  EVEX_W_0F11_P_1_M_1,
+  EVEX_W_0F11_P_2,
+  EVEX_W_0F11_P_3_M_0,
+  EVEX_W_0F11_P_3_M_1,
+  EVEX_W_0F12_P_0_M_0,
+  EVEX_W_0F12_P_0_M_1,
+  EVEX_W_0F12_P_1,
+  EVEX_W_0F12_P_2,
+  EVEX_W_0F12_P_3,
+  EVEX_W_0F13_P_0,
+  EVEX_W_0F13_P_2,
+  EVEX_W_0F14_P_0,
+  EVEX_W_0F14_P_2,
+  EVEX_W_0F15_P_0,
+  EVEX_W_0F15_P_2,
+  EVEX_W_0F16_P_0_M_0,
+  EVEX_W_0F16_P_0_M_1,
+  EVEX_W_0F16_P_1,
+  EVEX_W_0F16_P_2,
+  EVEX_W_0F17_P_0,
+  EVEX_W_0F17_P_2,
+  EVEX_W_0F28_P_0,
+  EVEX_W_0F28_P_2,
+  EVEX_W_0F29_P_0,
+  EVEX_W_0F29_P_2,
+  EVEX_W_0F2A_P_1,
+  EVEX_W_0F2A_P_3,
+  EVEX_W_0F2B_P_0,
+  EVEX_W_0F2B_P_2,
+  EVEX_W_0F2E_P_0,
+  EVEX_W_0F2E_P_2,
+  EVEX_W_0F2F_P_0,
+  EVEX_W_0F2F_P_2,
+  EVEX_W_0F51_P_0,
+  EVEX_W_0F51_P_1,
+  EVEX_W_0F51_P_2,
+  EVEX_W_0F51_P_3,
+  EVEX_W_0F54_P_0,
+  EVEX_W_0F54_P_2,
+  EVEX_W_0F55_P_0,
+  EVEX_W_0F55_P_2,
+  EVEX_W_0F56_P_0,
+  EVEX_W_0F56_P_2,
+  EVEX_W_0F57_P_0,
+  EVEX_W_0F57_P_2,
+  EVEX_W_0F58_P_0,
+  EVEX_W_0F58_P_1,
+  EVEX_W_0F58_P_2,
+  EVEX_W_0F58_P_3,
+  EVEX_W_0F59_P_0,
+  EVEX_W_0F59_P_1,
+  EVEX_W_0F59_P_2,
+  EVEX_W_0F59_P_3,
+  EVEX_W_0F5A_P_0,
+  EVEX_W_0F5A_P_1,
+  EVEX_W_0F5A_P_2,
+  EVEX_W_0F5A_P_3,
+  EVEX_W_0F5B_P_0,
+  EVEX_W_0F5B_P_1,
+  EVEX_W_0F5B_P_2,
+  EVEX_W_0F5C_P_0,
+  EVEX_W_0F5C_P_1,
+  EVEX_W_0F5C_P_2,
+  EVEX_W_0F5C_P_3,
+  EVEX_W_0F5D_P_0,
+  EVEX_W_0F5D_P_1,
+  EVEX_W_0F5D_P_2,
+  EVEX_W_0F5D_P_3,
+  EVEX_W_0F5E_P_0,
+  EVEX_W_0F5E_P_1,
+  EVEX_W_0F5E_P_2,
+  EVEX_W_0F5E_P_3,
+  EVEX_W_0F5F_P_0,
+  EVEX_W_0F5F_P_1,
+  EVEX_W_0F5F_P_2,
+  EVEX_W_0F5F_P_3,
+  EVEX_W_0F62_P_2,
+  EVEX_W_0F66_P_2,
+  EVEX_W_0F6A_P_2,
+  EVEX_W_0F6B_P_2,
+  EVEX_W_0F6C_P_2,
+  EVEX_W_0F6D_P_2,
+  EVEX_W_0F6E_P_2,
+  EVEX_W_0F6F_P_1,
+  EVEX_W_0F6F_P_2,
+  EVEX_W_0F6F_P_3,
+  EVEX_W_0F70_P_2,
+  EVEX_W_0F72_R_2_P_2,
+  EVEX_W_0F72_R_6_P_2,
+  EVEX_W_0F73_R_2_P_2,
+  EVEX_W_0F73_R_6_P_2,
+  EVEX_W_0F76_P_2,
+  EVEX_W_0F78_P_0,
+  EVEX_W_0F78_P_2,
+  EVEX_W_0F79_P_0,
+  EVEX_W_0F79_P_2,
+  EVEX_W_0F7A_P_1,
+  EVEX_W_0F7A_P_2,
+  EVEX_W_0F7A_P_3,
+  EVEX_W_0F7B_P_1,
+  EVEX_W_0F7B_P_2,
+  EVEX_W_0F7B_P_3,
+  EVEX_W_0F7E_P_1,
+  EVEX_W_0F7E_P_2,
+  EVEX_W_0F7F_P_1,
+  EVEX_W_0F7F_P_2,
+  EVEX_W_0F7F_P_3,
+  EVEX_W_0FC2_P_0,
+  EVEX_W_0FC2_P_1,
+  EVEX_W_0FC2_P_2,
+  EVEX_W_0FC2_P_3,
+  EVEX_W_0FC6_P_0,
+  EVEX_W_0FC6_P_2,
+  EVEX_W_0FD2_P_2,
+  EVEX_W_0FD3_P_2,
+  EVEX_W_0FD4_P_2,
+  EVEX_W_0FD6_P_2,
+  EVEX_W_0FE6_P_1,
+  EVEX_W_0FE6_P_2,
+  EVEX_W_0FE6_P_3,
+  EVEX_W_0FE7_P_2,
+  EVEX_W_0FF2_P_2,
+  EVEX_W_0FF3_P_2,
+  EVEX_W_0FF4_P_2,
+  EVEX_W_0FFA_P_2,
+  EVEX_W_0FFB_P_2,
+  EVEX_W_0FFE_P_2,
+  EVEX_W_0F380C_P_2,
+  EVEX_W_0F380D_P_2,
+  EVEX_W_0F3810_P_1,
+  EVEX_W_0F3810_P_2,
+  EVEX_W_0F3811_P_1,
+  EVEX_W_0F3811_P_2,
+  EVEX_W_0F3812_P_1,
+  EVEX_W_0F3812_P_2,
+  EVEX_W_0F3813_P_1,
+  EVEX_W_0F3813_P_2,
+  EVEX_W_0F3814_P_1,
+  EVEX_W_0F3815_P_1,
+  EVEX_W_0F3818_P_2,
+  EVEX_W_0F3819_P_2,
+  EVEX_W_0F381A_P_2,
+  EVEX_W_0F381B_P_2,
+  EVEX_W_0F381E_P_2,
+  EVEX_W_0F381F_P_2,
+  EVEX_W_0F3820_P_1,
+  EVEX_W_0F3821_P_1,
+  EVEX_W_0F3822_P_1,
+  EVEX_W_0F3823_P_1,
+  EVEX_W_0F3824_P_1,
+  EVEX_W_0F3825_P_1,
+  EVEX_W_0F3825_P_2,
+  EVEX_W_0F3826_P_1,
+  EVEX_W_0F3826_P_2,
+  EVEX_W_0F3828_P_1,
+  EVEX_W_0F3828_P_2,
+  EVEX_W_0F3829_P_1,
+  EVEX_W_0F3829_P_2,
+  EVEX_W_0F382A_P_1,
+  EVEX_W_0F382A_P_2,
+  EVEX_W_0F382B_P_2,
+  EVEX_W_0F3830_P_1,
+  EVEX_W_0F3831_P_1,
+  EVEX_W_0F3832_P_1,
+  EVEX_W_0F3833_P_1,
+  EVEX_W_0F3834_P_1,
+  EVEX_W_0F3835_P_1,
+  EVEX_W_0F3835_P_2,
+  EVEX_W_0F3837_P_2,
+  EVEX_W_0F3838_P_1,
+  EVEX_W_0F3839_P_1,
+  EVEX_W_0F383A_P_1,
+  EVEX_W_0F3840_P_2,
+  EVEX_W_0F3858_P_2,
+  EVEX_W_0F3859_P_2,
+  EVEX_W_0F385A_P_2,
+  EVEX_W_0F385B_P_2,
+  EVEX_W_0F3866_P_2,
+  EVEX_W_0F3875_P_2,
+  EVEX_W_0F3878_P_2,
+  EVEX_W_0F3879_P_2,
+  EVEX_W_0F387A_P_2,
+  EVEX_W_0F387B_P_2,
+  EVEX_W_0F387D_P_2,
+  EVEX_W_0F3883_P_2,
+  EVEX_W_0F388D_P_2,
+  EVEX_W_0F3891_P_2,
+  EVEX_W_0F3893_P_2,
+  EVEX_W_0F38A1_P_2,
+  EVEX_W_0F38A3_P_2,
+  EVEX_W_0F38C7_R_1_P_2,
+  EVEX_W_0F38C7_R_2_P_2,
+  EVEX_W_0F38C7_R_5_P_2,
+  EVEX_W_0F38C7_R_6_P_2,
+
+  EVEX_W_0F3A00_P_2,
+  EVEX_W_0F3A01_P_2,
+  EVEX_W_0F3A04_P_2,
+  EVEX_W_0F3A05_P_2,
+  EVEX_W_0F3A08_P_2,
+  EVEX_W_0F3A09_P_2,
+  EVEX_W_0F3A0A_P_2,
+  EVEX_W_0F3A0B_P_2,
+  EVEX_W_0F3A16_P_2,
+  EVEX_W_0F3A18_P_2,
+  EVEX_W_0F3A19_P_2,
+  EVEX_W_0F3A1A_P_2,
+  EVEX_W_0F3A1B_P_2,
+  EVEX_W_0F3A1D_P_2,
+  EVEX_W_0F3A21_P_2,
+  EVEX_W_0F3A22_P_2,
+  EVEX_W_0F3A23_P_2,
+  EVEX_W_0F3A38_P_2,
+  EVEX_W_0F3A39_P_2,
+  EVEX_W_0F3A3A_P_2,
+  EVEX_W_0F3A3B_P_2,
+  EVEX_W_0F3A3E_P_2,
+  EVEX_W_0F3A3F_P_2,
+  EVEX_W_0F3A42_P_2,
+  EVEX_W_0F3A43_P_2,
+  EVEX_W_0F3A50_P_2,
+  EVEX_W_0F3A51_P_2,
+  EVEX_W_0F3A56_P_2,
+  EVEX_W_0F3A57_P_2,
+  EVEX_W_0F3A66_P_2,
+  EVEX_W_0F3A67_P_2

 };
 
 typedef void (*op_rtn) (int bytemode, int sizeflag);
 };
 
 typedef void (*op_rtn) (int bytemode, int sizeflag);


@@ -1662,6 +2398,10 @@ struct dis386 {
    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise

+   "LW" => print 'd', 'q' depending on the VEX.W bit
+   "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
+          an operand size prefix, or suffix_always is true.  print
+          'q' if rex prefix is present.

 
    Many of the above letters print nothing in Intel mode.  See "putop"
    for the details.
 
    Many of the above letters print nothing in Intel mode.  See "putop"
    for the details.


@@ -1671,8 +2411,8 @@ struct dis386 {
 
 static const struct dis386 dis386[] = {
   /* 00 */
 
 static const struct dis386 dis386[] = {
   /* 00 */

-  { "addB",            { Eb, Gb } },
-  { "addS",            { Ev, Gv } },
+  { "addB",            { Ebh1, Gb } },
+  { "addS",            { Evh1, Gv } },

   { "addB",            { Gb, EbS } },
   { "addS",            { Gv, EvS } },
   { "addB",            { AL, Ib } },
   { "addB",            { Gb, EbS } },
   { "addS",            { Gv, EvS } },
   { "addB",            { AL, Ib } },


@@ -1680,8 +2420,8 @@ static const struct dis386 dis386[] = {
   { X86_64_TABLE (X86_64_06) },
   { X86_64_TABLE (X86_64_07) },
   /* 08 */
   { X86_64_TABLE (X86_64_06) },
   { X86_64_TABLE (X86_64_07) },
   /* 08 */

-  { "orB",             { Eb, Gb } },
-  { "orS",             { Ev, Gv } },
+  { "orB",             { Ebh1, Gb } },
+  { "orS",             { Evh1, Gv } },

   { "orB",             { Gb, EbS } },
   { "orS",             { Gv, EvS } },
   { "orB",             { AL, Ib } },
   { "orB",             { Gb, EbS } },
   { "orS",             { Gv, EvS } },
   { "orB",             { AL, Ib } },


@@ -1689,8 +2429,8 @@ static const struct dis386 dis386[] = {
   { X86_64_TABLE (X86_64_0D) },
   { Bad_Opcode },      /* 0x0f extended opcode escape */
   /* 10 */
   { X86_64_TABLE (X86_64_0D) },
   { Bad_Opcode },      /* 0x0f extended opcode escape */
   /* 10 */

-  { "adcB",            { Eb, Gb } },
-  { "adcS",            { Ev, Gv } },
+  { "adcB",            { Ebh1, Gb } },
+  { "adcS",            { Evh1, Gv } },

   { "adcB",            { Gb, EbS } },
   { "adcS",            { Gv, EvS } },
   { "adcB",            { AL, Ib } },
   { "adcB",            { Gb, EbS } },
   { "adcS",            { Gv, EvS } },
   { "adcB",            { AL, Ib } },


@@ -1698,8 +2438,8 @@ static const struct dis386 dis386[] = {
   { X86_64_TABLE (X86_64_16) },
   { X86_64_TABLE (X86_64_17) },
   /* 18 */
   { X86_64_TABLE (X86_64_16) },
   { X86_64_TABLE (X86_64_17) },
   /* 18 */

-  { "sbbB",            { Eb, Gb } },
-  { "sbbS",            { Ev, Gv } },
+  { "sbbB",            { Ebh1, Gb } },
+  { "sbbS",            { Evh1, Gv } },

   { "sbbB",            { Gb, EbS } },
   { "sbbS",            { Gv, EvS } },
   { "sbbB",            { AL, Ib } },
   { "sbbB",            { Gb, EbS } },
   { "sbbS",            { Gv, EvS } },
   { "sbbB",            { AL, Ib } },


@@ -1707,8 +2447,8 @@ static const struct dis386 dis386[] = {
   { X86_64_TABLE (X86_64_1E) },
   { X86_64_TABLE (X86_64_1F) },
   /* 20 */
   { X86_64_TABLE (X86_64_1E) },
   { X86_64_TABLE (X86_64_1F) },
   /* 20 */

-  { "andB",            { Eb, Gb } },
-  { "andS",            { Ev, Gv } },
+  { "andB",            { Ebh1, Gb } },
+  { "andS",            { Evh1, Gv } },

   { "andB",            { Gb, EbS } },
   { "andS",            { Gv, EvS } },
   { "andB",            { AL, Ib } },
   { "andB",            { Gb, EbS } },
   { "andS",            { Gv, EvS } },
   { "andB",            { AL, Ib } },


@@ -1716,8 +2456,8 @@ static const struct dis386 dis386[] = {
   { Bad_Opcode },      /* SEG ES prefix */
   { X86_64_TABLE (X86_64_27) },
   /* 28 */
   { Bad_Opcode },      /* SEG ES prefix */
   { X86_64_TABLE (X86_64_27) },
   /* 28 */

-  { "subB",            { Eb, Gb } },
-  { "subS",            { Ev, Gv } },
+  { "subB",            { Ebh1, Gb } },
+  { "subS",            { Evh1, Gv } },

   { "subB",            { Gb, EbS } },
   { "subS",            { Gv, EvS } },
   { "subB",            { AL, Ib } },
   { "subB",            { Gb, EbS } },
   { "subS",            { Gv, EvS } },
   { "subB",            { AL, Ib } },


@@ -1725,8 +2465,8 @@ static const struct dis386 dis386[] = {
   { Bad_Opcode },      /* SEG CS prefix */
   { X86_64_TABLE (X86_64_2F) },
   /* 30 */
   { Bad_Opcode },      /* SEG CS prefix */
   { X86_64_TABLE (X86_64_2F) },
   /* 30 */

-  { "xorB",            { Eb, Gb } },
-  { "xorS",            { Ev, Gv } },
+  { "xorB",            { Ebh1, Gb } },
+  { "xorS",            { Evh1, Gv } },

   { "xorB",            { Gb, EbS } },
   { "xorS",            { Gv, EvS } },
   { "xorB",            { AL, Ib } },
   { "xorB",            { Gb, EbS } },
   { "xorS",            { Gv, EvS } },
   { "xorB",            { AL, Ib } },


@@ -1790,30 +2530,30 @@ static const struct dis386 dis386[] = {
   /* 68 */
   { "pushT",           { sIv } },
   { "imulS",           { Gv, Ev, Iv } },
   /* 68 */
   { "pushT",           { sIv } },
   { "imulS",           { Gv, Ev, Iv } },

-  { "pushT",           { sIb } },
+  { "pushT",           { sIbT } },

   { "imulS",           { Gv, Ev, sIb } },
   { "ins{b|}",         { Ybr, indirDX } },
   { X86_64_TABLE (X86_64_6D) },
   { "outs{b|}",                { indirDXr, Xb } },
   { X86_64_TABLE (X86_64_6F) },
   /* 70 */
   { "imulS",           { Gv, Ev, sIb } },
   { "ins{b|}",         { Ybr, indirDX } },
   { X86_64_TABLE (X86_64_6D) },
   { "outs{b|}",                { indirDXr, Xb } },
   { X86_64_TABLE (X86_64_6F) },
   /* 70 */

-  { "joH",             { Jb, XX, cond_jump_flag } },
-  { "jnoH",            { Jb, XX, cond_jump_flag } },
-  { "jbH",             { Jb, XX, cond_jump_flag } },
-  { "jaeH",            { Jb, XX, cond_jump_flag } },
-  { "jeH",             { Jb, XX, cond_jump_flag } },
-  { "jneH",            { Jb, XX, cond_jump_flag } },
-  { "jbeH",            { Jb, XX, cond_jump_flag } },
-  { "jaH",             { Jb, XX, cond_jump_flag } },
+  { "joH",             { Jb, BND, cond_jump_flag } },
+  { "jnoH",            { Jb, BND, cond_jump_flag } },
+  { "jbH",             { Jb, BND, cond_jump_flag } },
+  { "jaeH",            { Jb, BND, cond_jump_flag } },
+  { "jeH",             { Jb, BND, cond_jump_flag } },
+  { "jneH",            { Jb, BND, cond_jump_flag } },
+  { "jbeH",            { Jb, BND, cond_jump_flag } },
+  { "jaH",             { Jb, BND, cond_jump_flag } },

   /* 78 */
   /* 78 */

-  { "jsH",             { Jb, XX, cond_jump_flag } },
-  { "jnsH",            { Jb, XX, cond_jump_flag } },
-  { "jpH",             { Jb, XX, cond_jump_flag } },
-  { "jnpH",            { Jb, XX, cond_jump_flag } },
-  { "jlH",             { Jb, XX, cond_jump_flag } },
-  { "jgeH",            { Jb, XX, cond_jump_flag } },
-  { "jleH",            { Jb, XX, cond_jump_flag } },
-  { "jgH",             { Jb, XX, cond_jump_flag } },
+  { "jsH",             { Jb, BND, cond_jump_flag } },
+  { "jnsH",            { Jb, BND, cond_jump_flag } },
+  { "jpH",             { Jb, BND, cond_jump_flag } },
+  { "jnpH",            { Jb, BND, cond_jump_flag } },
+  { "jlH",             { Jb, BND, cond_jump_flag } },
+  { "jgeH",            { Jb, BND, cond_jump_flag } },
+  { "jleH",            { Jb, BND, cond_jump_flag } },
+  { "jgH",             { Jb, BND, cond_jump_flag } },

   /* 80 */
   { REG_TABLE (REG_80) },
   { REG_TABLE (REG_81) },
   /* 80 */
   { REG_TABLE (REG_80) },
   { REG_TABLE (REG_81) },


@@ -1821,11 +2561,11 @@ static const struct dis386 dis386[] = {
   { REG_TABLE (REG_82) },
   { "testB",           { Eb, Gb } },
   { "testS",           { Ev, Gv } },
   { REG_TABLE (REG_82) },
   { "testB",           { Eb, Gb } },
   { "testS",           { Ev, Gv } },

-  { "xchgB",           { Eb, Gb } },
-  { "xchgS",           { Ev, Gv } },
+  { "xchgB",           { Ebh2, Gb } },
+  { "xchgS",           { Evh2, Gv } },

   /* 88 */
   /* 88 */

-  { "movB",            { Eb, Gb } },
-  { "movS",            { Ev, Gv } },
+  { "movB",            { Ebh3, Gb } },
+  { "movS",            { Evh3, Gv } },

   { "movB",            { Gb, EbS } },
   { "movS",            { Gv, EvS } },
   { "movD",            { Sv, Sw } },
   { "movB",            { Gb, EbS } },
   { "movS",            { Gv, EvS } },
   { "movD",            { Sv, Sw } },


@@ -1889,8 +2629,8 @@ static const struct dis386 dis386[] = {
   /* c0 */
   { REG_TABLE (REG_C0) },
   { REG_TABLE (REG_C1) },
   /* c0 */
   { REG_TABLE (REG_C0) },
   { REG_TABLE (REG_C1) },

-  { "retT",            { Iw } },
-  { "retT",            { XX } },
+  { "retT",            { Iw, BND } },
+  { "retT",            { BND } },

   { X86_64_TABLE (X86_64_C4) },
   { X86_64_TABLE (X86_64_C5) },
   { REG_TABLE (REG_C6) },
   { X86_64_TABLE (X86_64_C4) },
   { X86_64_TABLE (X86_64_C5) },
   { REG_TABLE (REG_C6) },


@@ -1903,7 +2643,7 @@ static const struct dis386 dis386[] = {
   { "int3",            { XX } },
   { "int",             { Ib } },
   { X86_64_TABLE (X86_64_CE) },
   { "int3",            { XX } },
   { "int",             { Ib } },
   { X86_64_TABLE (X86_64_CE) },

-  { "iretP",           { XX } },
+  { "iret%LP",         { XX } },

   /* d0 */
   { REG_TABLE (REG_D0) },
   { REG_TABLE (REG_D1) },
   /* d0 */
   { REG_TABLE (REG_D0) },
   { REG_TABLE (REG_D1) },


@@ -1932,10 +2672,10 @@ static const struct dis386 dis386[] = {
   { "outB",            { Ib, AL } },
   { "outG",            { Ib, zAX } },
   /* e8 */
   { "outB",            { Ib, AL } },
   { "outG",            { Ib, zAX } },
   /* e8 */

-  { "callT",           { Jv } },
-  { "jmpT",            { Jv } },
+  { "callT",           { Jv, BND } },
+  { "jmpT",            { Jv, BND } },

   { X86_64_TABLE (X86_64_EA) },
   { X86_64_TABLE (X86_64_EA) },

-  { "jmp",             { Jb } },
+  { "jmp",             { Jb, BND } },

   { "inB",             { AL, indirDX } },
   { "inG",             { zAX, indirDX } },
   { "outB",            { indirDX, AL } },
   { "inB",             { AL, indirDX } },
   { "inG",             { zAX, indirDX } },
   { "outB",            { indirDX, AL } },


@@ -1969,7 +2709,7 @@ static const struct dis386 dis386_twobyte[] = {
   { Bad_Opcode },
   { "syscall",         { XX } },
   { "clts",            { XX } },
   { Bad_Opcode },
   { "syscall",         { XX } },
   { "clts",            { XX } },

-  { "sysretP",         { XX } },
+  { "sysret%LP",               { XX } },

   /* 08 */
   { "invd",            { XX } },
   { "wbinvd",          { XX } },
   /* 08 */
   { "invd",            { XX } },
   { "wbinvd",          { XX } },


@@ -1991,17 +2731,17 @@ static const struct dis386 dis386_twobyte[] = {
   /* 18 */
   { REG_TABLE (REG_0F18) },
   { "nopQ",            { Ev } },
   /* 18 */
   { REG_TABLE (REG_0F18) },
   { "nopQ",            { Ev } },

-  { "nopQ",            { Ev } },
-  { "nopQ",            { Ev } },
+  { PREFIX_TABLE (PREFIX_0F1A) },
+  { PREFIX_TABLE (PREFIX_0F1B) },

   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   /* 20 */
   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   { "nopQ",            { Ev } },
   /* 20 */

-  { MOD_TABLE (MOD_0F20) },
-  { MOD_TABLE (MOD_0F21) },
-  { MOD_TABLE (MOD_0F22) },
-  { MOD_TABLE (MOD_0F23) },
+  { "movZ",            { Rm, Cm } },
+  { "movZ",            { Rm, Dm } },
+  { "movZ",            { Cm, Rm } },
+  { "movZ",            { Dm, Rm } },

   { MOD_TABLE (MOD_0F24) },
   { Bad_Opcode },
   { MOD_TABLE (MOD_0F26) },
   { MOD_TABLE (MOD_0F24) },
   { Bad_Opcode },
   { MOD_TABLE (MOD_0F26) },


@@ -2106,23 +2846,23 @@ static const struct dis386 dis386_twobyte[] = {
   { PREFIX_TABLE (PREFIX_0F7E) },
   { PREFIX_TABLE (PREFIX_0F7F) },
   /* 80 */
   { PREFIX_TABLE (PREFIX_0F7E) },
   { PREFIX_TABLE (PREFIX_0F7F) },
   /* 80 */

-  { "joH",             { Jv, XX, cond_jump_flag } },
-  { "jnoH",            { Jv, XX, cond_jump_flag } },
-  { "jbH",             { Jv, XX, cond_jump_flag } },
-  { "jaeH",            { Jv, XX, cond_jump_flag } },
-  { "jeH",             { Jv, XX, cond_jump_flag } },
-  { "jneH",            { Jv, XX, cond_jump_flag } },
-  { "jbeH",            { Jv, XX, cond_jump_flag } },
-  { "jaH",             { Jv, XX, cond_jump_flag } },
+  { "joH",             { Jv, BND, cond_jump_flag } },
+  { "jnoH",            { Jv, BND, cond_jump_flag } },
+  { "jbH",             { Jv, BND, cond_jump_flag } },
+  { "jaeH",            { Jv, BND, cond_jump_flag } },
+  { "jeH",             { Jv, BND, cond_jump_flag } },
+  { "jneH",            { Jv, BND, cond_jump_flag } },
+  { "jbeH",            { Jv, BND, cond_jump_flag } },
+  { "jaH",             { Jv, BND, cond_jump_flag } },

   /* 88 */
   /* 88 */

-  { "jsH",             { Jv, XX, cond_jump_flag } },
-  { "jnsH",            { Jv, XX, cond_jump_flag } },
-  { "jpH",             { Jv, XX, cond_jump_flag } },
-  { "jnpH",            { Jv, XX, cond_jump_flag } },
-  { "jlH",             { Jv, XX, cond_jump_flag } },
-  { "jgeH",            { Jv, XX, cond_jump_flag } },
-  { "jleH",            { Jv, XX, cond_jump_flag } },
-  { "jgH",             { Jv, XX, cond_jump_flag } },
+  { "jsH",             { Jv, BND, cond_jump_flag } },
+  { "jnsH",            { Jv, BND, cond_jump_flag } },
+  { "jpH",             { Jv, BND, cond_jump_flag } },
+  { "jnpH",            { Jv, BND, cond_jump_flag } },
+  { "jlH",             { Jv, BND, cond_jump_flag } },
+  { "jgeH",            { Jv, BND, cond_jump_flag } },
+  { "jleH",            { Jv, BND, cond_jump_flag } },
+  { "jgH",             { Jv, BND, cond_jump_flag } },

   /* 90 */
   { "seto",            { Eb } },
   { "setno",           { Eb } },
   /* 90 */
   { "seto",            { Eb } },
   { "setno",           { Eb } },


@@ -2154,16 +2894,16 @@ static const struct dis386 dis386_twobyte[] = {
   { "pushT",           { gs } },
   { "popT",            { gs } },
   { "rsm",             { XX } },
   { "pushT",           { gs } },
   { "popT",            { gs } },
   { "rsm",             { XX } },

-  { "btsS",            { Ev, Gv } },
+  { "btsS",            { Evh1, Gv } },

   { "shrdS",           { Ev, Gv, Ib } },
   { "shrdS",           { Ev, Gv, CL } },
   { REG_TABLE (REG_0FAE) },
   { "imulS",           { Gv, Ev } },
   /* b0 */
   { "shrdS",           { Ev, Gv, Ib } },
   { "shrdS",           { Ev, Gv, CL } },
   { REG_TABLE (REG_0FAE) },
   { "imulS",           { Gv, Ev } },
   /* b0 */

-  { "cmpxchgB",                { Eb, Gb } },
-  { "cmpxchgS",                { Ev, Gv } },
+  { "cmpxchgB",                { Ebh1, Gb } },
+  { "cmpxchgS",                { Evh1, Gv } },

   { MOD_TABLE (MOD_0FB2) },
   { MOD_TABLE (MOD_0FB2) },

-  { "btrS",            { Ev, Gv } },
+  { "btrS",            { Evh1, Gv } },

   { MOD_TABLE (MOD_0FB4) },
   { MOD_TABLE (MOD_0FB5) },
   { "movz{bR|x}",      { Gv, Eb } },
   { MOD_TABLE (MOD_0FB4) },
   { MOD_TABLE (MOD_0FB5) },
   { "movz{bR|x}",      { Gv, Eb } },


@@ -2172,14 +2912,14 @@ static const struct dis386 dis386_twobyte[] = {
   { PREFIX_TABLE (PREFIX_0FB8) },
   { "ud1",             { XX } },
   { REG_TABLE (REG_0FBA) },
   { PREFIX_TABLE (PREFIX_0FB8) },
   { "ud1",             { XX } },
   { REG_TABLE (REG_0FBA) },

-  { "btcS",            { Ev, Gv } },
+  { "btcS",            { Evh1, Gv } },

   { PREFIX_TABLE (PREFIX_0FBC) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",      { Gv, Eb } },
   { "movs{wR|x}",      { Gv, Ew } }, /* yes, there really is movsww ! */
   /* c0 */
   { PREFIX_TABLE (PREFIX_0FBC) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",      { Gv, Eb } },
   { "movs{wR|x}",      { Gv, Ew } }, /* yes, there really is movsww ! */
   /* c0 */

-  { "xaddB",           { Eb, Gb } },
-  { "xaddS",           { Ev, Gv } },
+  { "xaddB",           { Ebh1, Gb } },
+  { "xaddS",           { Evh1, Gv } },

   { PREFIX_TABLE (PREFIX_0FC2) },
   { PREFIX_TABLE (PREFIX_0FC3) },
   { "pinsrw",          { MX, Edqw, Ib } },
   { PREFIX_TABLE (PREFIX_0FC2) },
   { PREFIX_TABLE (PREFIX_0FC3) },
   { "pinsrw",          { MX, Edqw, Ib } },


@@ -2297,6 +3037,29 @@ static const unsigned char twobyte_has_modrm[256] = {
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
 };
 
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
 };
 

+static const unsigned char twobyte_has_mandatory_prefix[256] = {
+  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
+  /*       -------------------------------        */
+  /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
+  /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
+  /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
+  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
+  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
+  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
+  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
+  /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
+  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
+  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
+  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
+  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
+  /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
+  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
+  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
+  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
+  /*       -------------------------------        */
+  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
+};
+

 static char obuf[100];
 static char *obufp;
 static char *mnemonicendp;
 static char obuf[100];
 static char *obufp;
 static char *mnemonicendp;


@@ -2304,6 +3067,7 @@ static char scratchbuf[100];
 static unsigned char *start_codep;
 static unsigned char *insn_codep;
 static unsigned char *codep;
 static unsigned char *start_codep;
 static unsigned char *insn_codep;
 static unsigned char *codep;

+static unsigned char *end_codep;

 static int last_lock_prefix;
 static int last_repz_prefix;
 static int last_repnz_prefix;
 static int last_lock_prefix;
 static int last_repz_prefix;
 static int last_repnz_prefix;


@@ -2311,6 +3075,11 @@ static int last_data_prefix;
 static int last_addr_prefix;
 static int last_rex_prefix;
 static int last_seg_prefix;
 static int last_addr_prefix;
 static int last_rex_prefix;
 static int last_seg_prefix;

+static int fwait_prefix;
+/* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
+static int mandatory_prefix;
+/* The active segment register prefix.  */
+static int active_seg_prefix;

 #define MAX_CODE_LENGTH 15
 /* We can up to 14 prefixes since the maximum instruction length is
    15bytes.  */
 #define MAX_CODE_LENGTH 15
 /* We can up to 14 prefixes since the maximum instruction length is
    15bytes.  */


@@ -2337,6 +3106,13 @@ static struct
     int length;
     int prefix;
     int w;
     int length;
     int prefix;
     int w;

+    int evex;
+    int r;
+    int v;
+    int mask_register_specifier;
+    int zeroing;
+    int ll;
+    int b;

   }
 vex;
 static unsigned char need_vex;
   }
 vex;
 static unsigned char need_vex;


@@ -2363,6 +3139,7 @@ static const char **names_seg;
 static const char *index64;
 static const char *index32;
 static const char **index16;
 static const char *index64;
 static const char *index32;
 static const char **index16;

+static const char **names_bnd;

 
 static const char *intel_names64[] = {
   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
 
 static const char *intel_names64[] = {
   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",


@@ -2430,18 +3207,34 @@ static const char *att_names_mm[] = {
   "%mm4", "%mm5", "%mm6", "%mm7"
 };
 
   "%mm4", "%mm5", "%mm6", "%mm7"
 };
 

+static const char *intel_names_bnd[] = {
+  "bnd0", "bnd1", "bnd2", "bnd3"
+};
+
+static const char *att_names_bnd[] = {
+  "%bnd0", "%bnd1", "%bnd2", "%bnd3"
+};
+

 static const char **names_xmm;
 static const char *intel_names_xmm[] = {
   "xmm0", "xmm1", "xmm2", "xmm3",
   "xmm4", "xmm5", "xmm6", "xmm7",
   "xmm8", "xmm9", "xmm10", "xmm11",
 static const char **names_xmm;
 static const char *intel_names_xmm[] = {
   "xmm0", "xmm1", "xmm2", "xmm3",
   "xmm4", "xmm5", "xmm6", "xmm7",
   "xmm8", "xmm9", "xmm10", "xmm11",

-  "xmm12", "xmm13", "xmm14", "xmm15"
+  "xmm12", "xmm13", "xmm14", "xmm15",
+  "xmm16", "xmm17", "xmm18", "xmm19",
+  "xmm20", "xmm21", "xmm22", "xmm23",
+  "xmm24", "xmm25", "xmm26", "xmm27",
+  "xmm28", "xmm29", "xmm30", "xmm31"

 };
 static const char *att_names_xmm[] = {
   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
 };
 static const char *att_names_xmm[] = {
   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
   "%xmm8", "%xmm9", "%xmm10", "%xmm11",

-  "%xmm12", "%xmm13", "%xmm14", "%xmm15"
+  "%xmm12", "%xmm13", "%xmm14", "%xmm15",
+  "%xmm16", "%xmm17", "%xmm18", "%xmm19",
+  "%xmm20", "%xmm21", "%xmm22", "%xmm23",
+  "%xmm24", "%xmm25", "%xmm26", "%xmm27",
+  "%xmm28", "%xmm29", "%xmm30", "%xmm31"

 };
 
 static const char **names_ymm;
 };
 
 static const char **names_ymm;


@@ -2449,47 +3242,93 @@ static const char *intel_names_ymm[] = {
   "ymm0", "ymm1", "ymm2", "ymm3",
   "ymm4", "ymm5", "ymm6", "ymm7",
   "ymm8", "ymm9", "ymm10", "ymm11",
   "ymm0", "ymm1", "ymm2", "ymm3",
   "ymm4", "ymm5", "ymm6", "ymm7",
   "ymm8", "ymm9", "ymm10", "ymm11",

-  "ymm12", "ymm13", "ymm14", "ymm15"
+  "ymm12", "ymm13", "ymm14", "ymm15",
+  "ymm16", "ymm17", "ymm18", "ymm19",
+  "ymm20", "ymm21", "ymm22", "ymm23",
+  "ymm24", "ymm25", "ymm26", "ymm27",
+  "ymm28", "ymm29", "ymm30", "ymm31"

 };
 static const char *att_names_ymm[] = {
   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
 };
 static const char *att_names_ymm[] = {
   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
   "%ymm8", "%ymm9", "%ymm10", "%ymm11",

-  "%ymm12", "%ymm13", "%ymm14", "%ymm15"
+  "%ymm12", "%ymm13", "%ymm14", "%ymm15",
+  "%ymm16", "%ymm17", "%ymm18", "%ymm19",
+  "%ymm20", "%ymm21", "%ymm22", "%ymm23",
+  "%ymm24", "%ymm25", "%ymm26", "%ymm27",
+  "%ymm28", "%ymm29", "%ymm30", "%ymm31"
+};
+
+static const char **names_zmm;
+static const char *intel_names_zmm[] = {
+  "zmm0", "zmm1", "zmm2", "zmm3",
+  "zmm4", "zmm5", "zmm6", "zmm7",
+  "zmm8", "zmm9", "zmm10", "zmm11",
+  "zmm12", "zmm13", "zmm14", "zmm15",
+  "zmm16", "zmm17", "zmm18", "zmm19",
+  "zmm20", "zmm21", "zmm22", "zmm23",
+  "zmm24", "zmm25", "zmm26", "zmm27",
+  "zmm28", "zmm29", "zmm30", "zmm31"
+};
+static const char *att_names_zmm[] = {
+  "%zmm0", "%zmm1", "%zmm2", "%zmm3",
+  "%zmm4", "%zmm5", "%zmm6", "%zmm7",
+  "%zmm8", "%zmm9", "%zmm10", "%zmm11",
+  "%zmm12", "%zmm13", "%zmm14", "%zmm15",
+  "%zmm16", "%zmm17", "%zmm18", "%zmm19",
+  "%zmm20", "%zmm21", "%zmm22", "%zmm23",
+  "%zmm24", "%zmm25", "%zmm26", "%zmm27",
+  "%zmm28", "%zmm29", "%zmm30", "%zmm31"
+};
+
+static const char **names_mask;
+static const char *intel_names_mask[] = {
+  "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
+};
+static const char *att_names_mask[] = {
+  "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
+};
+
+static const char *names_rounding[] =
+{
+  "{rn-sae}",
+  "{rd-sae}",
+  "{ru-sae}",
+  "{rz-sae}"

 };
 
 static const struct dis386 reg_table[][8] = {
   /* REG_80 */
   {
 };
 
 static const struct dis386 reg_table[][8] = {
   /* REG_80 */
   {

-    { "addA",  { Eb, Ib } },
-    { "orA",   { Eb, Ib } },
-    { "adcA",  { Eb, Ib } },
-    { "sbbA",  { Eb, Ib } },
-    { "andA",  { Eb, Ib } },
-    { "subA",  { Eb, Ib } },
-    { "xorA",  { Eb, Ib } },
+    { "addA",  { Ebh1, Ib } },
+    { "orA",   { Ebh1, Ib } },
+    { "adcA",  { Ebh1, Ib } },
+    { "sbbA",  { Ebh1, Ib } },
+    { "andA",  { Ebh1, Ib } },
+    { "subA",  { Ebh1, Ib } },
+    { "xorA",  { Ebh1, Ib } },

     { "cmpA",  { Eb, Ib } },
   },
   /* REG_81 */
   {
     { "cmpA",  { Eb, Ib } },
   },
   /* REG_81 */
   {

-    { "addQ",  { Ev, Iv } },
-    { "orQ",   { Ev, Iv } },
-    { "adcQ",  { Ev, Iv } },
-    { "sbbQ",  { Ev, Iv } },
-    { "andQ",  { Ev, Iv } },
-    { "subQ",  { Ev, Iv } },
-    { "xorQ",  { Ev, Iv } },
+    { "addQ",  { Evh1, Iv } },
+    { "orQ",   { Evh1, Iv } },
+    { "adcQ",  { Evh1, Iv } },
+    { "sbbQ",  { Evh1, Iv } },
+    { "andQ",  { Evh1, Iv } },
+    { "subQ",  { Evh1, Iv } },
+    { "xorQ",  { Evh1, Iv } },

     { "cmpQ",  { Ev, Iv } },
   },
   /* REG_82 */
   {
     { "cmpQ",  { Ev, Iv } },
   },
   /* REG_82 */
   {

-    { "addQ",  { Ev, sIb } },
-    { "orQ",   { Ev, sIb } },
-    { "adcQ",  { Ev, sIb } },
-    { "sbbQ",  { Ev, sIb } },
-    { "andQ",  { Ev, sIb } },
-    { "subQ",  { Ev, sIb } },
-    { "xorQ",  { Ev, sIb } },
+    { "addQ",  { Evh1, sIb } },
+    { "orQ",   { Evh1, sIb } },
+    { "adcQ",  { Evh1, sIb } },
+    { "sbbQ",  { Evh1, sIb } },
+    { "andQ",  { Evh1, sIb } },
+    { "subQ",  { Evh1, sIb } },
+    { "xorQ",  { Evh1, sIb } },

     { "cmpQ",  { Ev, sIb } },
   },
   /* REG_8F */
     { "cmpQ",  { Ev, sIb } },
   },
   /* REG_8F */


@@ -2525,11 +3364,25 @@ static const struct dis386 reg_table[][8] = {
   },
   /* REG_C6 */
   {
   },
   /* REG_C6 */
   {

-    { "movA",  { Eb, Ib } },
+    { "movA",  { Ebh3, Ib } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_C6_REG_7) },

   },
   /* REG_C7 */
   {
   },
   /* REG_C7 */
   {

-    { "movQ",  { Ev, Iv } },
+    { "movQ",  { Evh3, Iv } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_C7_REG_7) },

   },
   /* REG_D0 */
   {
   },
   /* REG_D0 */
   {


@@ -2579,8 +3432,8 @@ static const struct dis386 reg_table[][8] = {
   {
     { "testA", { Eb, Ib } },
     { Bad_Opcode },
   {
     { "testA", { Eb, Ib } },
     { Bad_Opcode },

-    { "notA",  { Eb } },
-    { "negA",  { Eb } },
+    { "notA",  { Ebh1 } },
+    { "negA",  { Ebh1 } },

     { "mulA",  { Eb } },       /* Don't print the implicit %al register,  */
     { "imulA", { Eb } },       /* to distinguish these opcodes from other */
     { "divA",  { Eb } },       /* mul/imul opcodes.  Do the same for div  */
     { "mulA",  { Eb } },       /* Don't print the implicit %al register,  */
     { "imulA", { Eb } },       /* to distinguish these opcodes from other */
     { "divA",  { Eb } },       /* mul/imul opcodes.  Do the same for div  */


@@ -2590,8 +3443,8 @@ static const struct dis386 reg_table[][8] = {
   {
     { "testQ", { Ev, Iv } },
     { Bad_Opcode },
   {
     { "testQ", { Ev, Iv } },
     { Bad_Opcode },

-    { "notQ",  { Ev } },
-    { "negQ",  { Ev } },
+    { "notQ",  { Evh1 } },
+    { "negQ",  { Evh1 } },

     { "mulQ",  { Ev } },       /* Don't print the implicit register.  */
     { "imulQ", { Ev } },
     { "divQ",  { Ev } },
     { "mulQ",  { Ev } },       /* Don't print the implicit register.  */
     { "imulQ", { Ev } },
     { "divQ",  { Ev } },


@@ -2599,17 +3452,17 @@ static const struct dis386 reg_table[][8] = {
   },
   /* REG_FE */
   {
   },
   /* REG_FE */
   {

-    { "incA",  { Eb } },
-    { "decA",  { Eb } },
+    { "incA",  { Ebh1 } },
+    { "decA",  { Ebh1 } },

   },
   /* REG_FF */
   {
   },
   /* REG_FF */
   {

-    { "incQ",  { Ev } },
-    { "decQ",  { Ev } },
-    { "call{T|}", { indirEv } },
-    { "Jcall{T|}", { indirEp } },
-    { "jmp{T|}", { indirEv } },
-    { "Jjmp{T|}", { indirEp } },
+    { "incQ",  { Evh1 } },
+    { "decQ",  { Evh1 } },
+    { "call{T|}", { indirEv, BND } },
+    { MOD_TABLE (MOD_FF_REG_3) },
+    { "jmp{T|}", { indirEv, BND } },
+    { MOD_TABLE (MOD_FF_REG_5) },

     { "pushU", { stackEv } },
     { Bad_Opcode },
   },
     { "pushU", { stackEv } },
     { Bad_Opcode },
   },


@@ -2639,6 +3492,12 @@ static const struct dis386 reg_table[][8] = {
   {
     { "prefetch",      { Mb } },
     { "prefetchw",     { Mb } },
   {
     { "prefetch",      { Mb } },
     { "prefetchw",     { Mb } },

+    { "prefetchwt1",   { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },

   },
   /* REG_0F18 */
   {
   },
   /* REG_0F18 */
   {


@@ -2646,6 +3505,10 @@ static const struct dis386 reg_table[][8] = {
     { MOD_TABLE (MOD_0F18_REG_1) },
     { MOD_TABLE (MOD_0F18_REG_2) },
     { MOD_TABLE (MOD_0F18_REG_3) },
     { MOD_TABLE (MOD_0F18_REG_1) },
     { MOD_TABLE (MOD_0F18_REG_2) },
     { MOD_TABLE (MOD_0F18_REG_3) },

+    { MOD_TABLE (MOD_0F18_REG_4) },
+    { MOD_TABLE (MOD_0F18_REG_5) },
+    { MOD_TABLE (MOD_0F18_REG_6) },
+    { MOD_TABLE (MOD_0F18_REG_7) },

   },
   /* REG_0F71 */
   {
   },
   /* REG_0F71 */
   {


@@ -2711,18 +3574,18 @@ static const struct dis386 reg_table[][8] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { "btQ",   { Ev, Ib } },
     { Bad_Opcode },
     { Bad_Opcode },
     { "btQ",   { Ev, Ib } },

-    { "btsQ",  { Ev, Ib } },
-    { "btrQ",  { Ev, Ib } },
-    { "btcQ",  { Ev, Ib } },
+    { "btsQ",  { Evh1, Ib } },
+    { "btrQ",  { Evh1, Ib } },
+    { "btcQ",  { Evh1, Ib } },

   },
   /* REG_0FC7 */
   {
     { Bad_Opcode },
     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
     { Bad_Opcode },
   },
   /* REG_0FC7 */
   {
     { Bad_Opcode },
     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { MOD_TABLE (MOD_0FC7_REG_3) },
+    { MOD_TABLE (MOD_0FC7_REG_4) },
+    { MOD_TABLE (MOD_0FC7_REG_5) },

     { MOD_TABLE (MOD_0FC7_REG_6) },
     { MOD_TABLE (MOD_0FC7_REG_7) },
   },
     { MOD_TABLE (MOD_0FC7_REG_6) },
     { MOD_TABLE (MOD_0FC7_REG_7) },
   },


@@ -2802,6 +3665,9 @@ static const struct dis386 reg_table[][8] = {
     { Bad_Opcode },
     { "blci",  { { OP_LWP_E, 0 }, Ev } },
   },
     { Bad_Opcode },
     { "blci",  { { OP_LWP_E, 0 }, Ev } },
   },

+#define NEED_REG_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_REG_TABLE

 };
 
 static const struct dis386 prefix_table[][4] = {
 };
 
 static const struct dis386 prefix_table[][4] = {


@@ -2843,6 +3709,22 @@ static const struct dis386 prefix_table[][4] = {
     { "movhpd",        { XM, EXq } },
   },
 
     { "movhpd",        { XM, EXq } },
   },
 

+  /* PREFIX_0F1A */
+  {
+    { MOD_TABLE (MOD_0F1A_PREFIX_0) },
+    { "bndcl",  { Gbnd, Ev_bnd } },
+    { "bndmov", { Gbnd, Ebnd } },
+    { "bndcu",  { Gbnd, Ev_bnd } },
+  },
+
+  /* PREFIX_0F1B */
+  {
+    { MOD_TABLE (MOD_0F1B_PREFIX_0) },
+    { MOD_TABLE (MOD_0F1B_PREFIX_1) },
+    { "bndmov", { Ebnd, Gbnd } },
+    { "bndcn",  { Gbnd, Ev_bnd } },
+  },
+

   /* PREFIX_0F2A */
   {
     { "cvtpi2ps", { XM, EMCq } },
   /* PREFIX_0F2A */
   {
     { "cvtpi2ps", { XM, EMCq } },


@@ -2877,9 +3759,9 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_0F2E */
   {
 
   /* PREFIX_0F2E */
   {

-    { "ucomiss",{ XM, EXd } }, 
+    { "ucomiss",{ XM, EXd } },

     { Bad_Opcode },
     { Bad_Opcode },

-    { "ucomisd",{ XM, EXq } }, 
+    { "ucomisd",{ XM, EXq } },

   },
 
   /* PREFIX_0F2F */
   },
 
   /* PREFIX_0F2F */


@@ -3106,6 +3988,27 @@ static const struct dis386 prefix_table[][4] = {
     { "wrgsbase", { Ev } },
   },
 
     { "wrgsbase", { Ev } },
   },
 

+  /* PREFIX_0FAE_REG_6 */
+  {
+    { "xsaveopt",      { FXSAVE } },
+    { Bad_Opcode },
+    { "clwb",  { Mb } },
+  },
+
+  /* PREFIX_0FAE_REG_7 */
+  {
+    { "clflush",       { Mb } },
+    { Bad_Opcode },
+    { "clflushopt",    { Mb } },
+  },
+
+  /* PREFIX_RM_0_0FAE_REG_7 */
+  {
+    { "sfence",                { Skip_MODRM } },
+    { Bad_Opcode },
+    { "pcommit",               { Skip_MODRM } },
+  },
+

   /* PREFIX_0FB8 */
   {
     { Bad_Opcode },
   /* PREFIX_0FB8 */
   {
     { Bad_Opcode },


@@ -3423,6 +4326,43 @@ static const struct dis386 prefix_table[][4] = {
     { "invvpid", { Gm, Mo } },
   },
 
     { "invvpid", { Gm, Mo } },
   },
 

+  /* PREFIX_0F3882 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "invpcid", { Gm, M } },
+  },
+
+  /* PREFIX_0F38C8 */
+  {
+    { "sha1nexte", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38C9 */
+  {
+    { "sha1msg1", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CA */
+  {
+    { "sha1msg2", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CB */
+  {
+    { "sha256rnds2", { XM, EXxmm, XMM0 } },
+  },
+
+  /* PREFIX_0F38CC */
+  {
+    { "sha256msg1", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CD */
+  {
+    { "sha256msg2", { XM, EXxmm } },
+  },
+

   /* PREFIX_0F38DB */
   {
     { Bad_Opcode },
   /* PREFIX_0F38DB */
   {
     { Bad_Opcode },


@@ -3463,7 +4403,7 @@ static const struct dis386 prefix_table[][4] = {
     { "movbeS",        { Gv, { MOVBE_Fixup, v_mode } } },
     { Bad_Opcode },
     { "movbeS",        { Gv, { MOVBE_Fixup, v_mode } } },
     { "movbeS",        { Gv, { MOVBE_Fixup, v_mode } } },
     { Bad_Opcode },
     { "movbeS",        { Gv, { MOVBE_Fixup, v_mode } } },

-    { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },     
+    { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },

   },
 
   /* PREFIX_0F38F1 */
   },
 
   /* PREFIX_0F38F1 */


@@ -3471,7 +4411,15 @@ static const struct dis386 prefix_table[][4] = {
     { "movbeS",        { { MOVBE_Fixup, v_mode }, Gv } },
     { Bad_Opcode },
     { "movbeS",        { { MOVBE_Fixup, v_mode }, Gv } },
     { "movbeS",        { { MOVBE_Fixup, v_mode }, Gv } },
     { Bad_Opcode },
     { "movbeS",        { { MOVBE_Fixup, v_mode }, Gv } },

-    { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },     
+    { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
+  },
+
+  /* PREFIX_0F38F6 */
+  {
+    { Bad_Opcode },
+    { "adoxS", { Gdq, Edq} },
+    { "adcxS", { Gdq, Edq} },
+    { Bad_Opcode },

   },
 
   /* PREFIX_0F3A08 */
   },
 
   /* PREFIX_0F3A08 */


@@ -3628,6 +4576,11 @@ static const struct dis386 prefix_table[][4] = {
     { "pcmpistri", { XM, EXx, Ib } },
   },
 
     { "pcmpistri", { XM, EXx, Ib } },
   },
 

+  /* PREFIX_0F3ACC */
+  {
+    { "sha1rnds4", { XM, EXxmm, Ib } },
+  },
+

   /* PREFIX_0F3ADF */
   {
     { Bad_Opcode },
   /* PREFIX_0F3ADF */
   {
     { Bad_Opcode },


@@ -3704,6 +4657,62 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
   },
 
     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
   },
 

+  /* PREFIX_VEX_0F41 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
+  },
+
+  /* PREFIX_VEX_0F42 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
+  },
+
+  /* PREFIX_VEX_0F44 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
+  },
+
+  /* PREFIX_VEX_0F45 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
+  },
+
+  /* PREFIX_VEX_0F46 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
+  },
+
+  /* PREFIX_VEX_0F47 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
+  },
+
+  /* PREFIX_VEX_0F4A */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
+  },
+
+  /* PREFIX_VEX_0F4B */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
+  },
+

   /* PREFIX_VEX_0F51 */
   {
     { VEX_W_TABLE (VEX_W_0F51_P_0) },
   /* PREFIX_VEX_0F51 */
   {
     { VEX_W_TABLE (VEX_W_0F51_P_0) },


@@ -3791,98 +4800,98 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) },
+    { VEX_W_TABLE (VEX_W_0F60_P_2) },

   },
 
   /* PREFIX_VEX_0F61 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F61 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) },
+    { VEX_W_TABLE (VEX_W_0F61_P_2) },

   },
 
   /* PREFIX_VEX_0F62 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F62 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) },
+    { VEX_W_TABLE (VEX_W_0F62_P_2) },

   },
 
   /* PREFIX_VEX_0F63 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F63 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) },
+    { VEX_W_TABLE (VEX_W_0F63_P_2) },

   },
 
   /* PREFIX_VEX_0F64 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F64 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) },
+    { VEX_W_TABLE (VEX_W_0F64_P_2) },

   },
 
   /* PREFIX_VEX_0F65 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F65 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) },
+    { VEX_W_TABLE (VEX_W_0F65_P_2) },

   },
 
   /* PREFIX_VEX_0F66 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F66 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) },
+    { VEX_W_TABLE (VEX_W_0F66_P_2) },

   },
 
   /* PREFIX_VEX_0F67 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F67 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) },
+    { VEX_W_TABLE (VEX_W_0F67_P_2) },

   },
 
   /* PREFIX_VEX_0F68 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F68 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) },
+    { VEX_W_TABLE (VEX_W_0F68_P_2) },

   },
 
   /* PREFIX_VEX_0F69 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F69 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) },
+    { VEX_W_TABLE (VEX_W_0F69_P_2) },

   },
 
   /* PREFIX_VEX_0F6A */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F6A */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) },
+    { VEX_W_TABLE (VEX_W_0F6A_P_2) },

   },
 
   /* PREFIX_VEX_0F6B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F6B */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F6B_P_2) },

   },
 
   /* PREFIX_VEX_0F6C */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F6C */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) },
+    { VEX_W_TABLE (VEX_W_0F6C_P_2) },

   },
 
   /* PREFIX_VEX_0F6D */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F6D */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) },
+    { VEX_W_TABLE (VEX_W_0F6D_P_2) },

   },
 
   /* PREFIX_VEX_0F6E */
   },
 
   /* PREFIX_VEX_0F6E */


@@ -3902,100 +4911,100 @@ static const struct dis386 prefix_table[][4] = {
   /* PREFIX_VEX_0F70 */
   {
     { Bad_Opcode },
   /* PREFIX_VEX_0F70 */
   {
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) },
-    { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) },
-    { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) },
+    { VEX_W_TABLE (VEX_W_0F70_P_1) },
+    { VEX_W_TABLE (VEX_W_0F70_P_2) },
+    { VEX_W_TABLE (VEX_W_0F70_P_3) },

   },
 
   /* PREFIX_VEX_0F71_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F71_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) },
+    { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },

   },
 
   /* PREFIX_VEX_0F71_REG_4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F71_REG_4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) },
+    { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },

   },
 
   /* PREFIX_VEX_0F71_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F71_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) },
+    { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },

   },
 
   /* PREFIX_VEX_0F72_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F72_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) },
+    { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },

   },
 
   /* PREFIX_VEX_0F72_REG_4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F72_REG_4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) },
+    { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },

   },
 
   /* PREFIX_VEX_0F72_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F72_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) },
+    { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },

   },
 
   /* PREFIX_VEX_0F73_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F73_REG_2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) },
+    { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },

   },
 
   /* PREFIX_VEX_0F73_REG_3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F73_REG_3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) },
+    { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },

   },
 
   /* PREFIX_VEX_0F73_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F73_REG_6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) },
+    { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },

   },
 
   /* PREFIX_VEX_0F73_REG_7 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F73_REG_7 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) },
+    { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },

   },
 
   /* PREFIX_VEX_0F74 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F74 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) },
+    { VEX_W_TABLE (VEX_W_0F74_P_2) },

   },
 
   /* PREFIX_VEX_0F75 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F75 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) },
+    { VEX_W_TABLE (VEX_W_0F75_P_2) },

   },
 
   /* PREFIX_VEX_0F76 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F76 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) },
+    { VEX_W_TABLE (VEX_W_0F76_P_2) },

   },
 
   /* PREFIX_VEX_0F77 */
   },
 
   /* PREFIX_VEX_0F77 */


@@ -4033,6 +5042,50 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
   },
 

+  /* PREFIX_VEX_0F90 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
+  },
+
+  /* PREFIX_VEX_0F91 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
+  },
+
+  /* PREFIX_VEX_0F92 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
+    { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
+  },
+
+  /* PREFIX_VEX_0F93 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
+    { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
+  },
+
+  /* PREFIX_VEX_0F98 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
+  },
+
+  /* PREFIX_VEX_0F99 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
+  },
+

   /* PREFIX_VEX_0FC2 */
   {
     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
   /* PREFIX_VEX_0FC2 */
   {
     { VEX_W_TABLE (VEX_W_0FC2_P_0) },


@@ -4067,35 +5120,35 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD1_P_2) },

   },
 
   /* PREFIX_VEX_0FD2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FD2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD2_P_2) },

   },
 
   /* PREFIX_VEX_0FD3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FD3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD3_P_2) },

   },
 
   /* PREFIX_VEX_0FD4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FD4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD4_P_2) },

   },
 
   /* PREFIX_VEX_0FD5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FD5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD5_P_2) },

   },
 
   /* PREFIX_VEX_0FD6 */
   },
 
   /* PREFIX_VEX_0FD6 */


@@ -4116,98 +5169,98 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD8_P_2) },

   },
 
   /* PREFIX_VEX_0FD9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FD9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD9_P_2) },

   },
 
   /* PREFIX_VEX_0FDA */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDA */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDA_P_2) },

   },
 
   /* PREFIX_VEX_0FDB */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDB */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDB_P_2) },

   },
 
   /* PREFIX_VEX_0FDC */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDC */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDC_P_2) },

   },
 
   /* PREFIX_VEX_0FDD */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDD */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDD_P_2) },

   },
 
   /* PREFIX_VEX_0FDE */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDE */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDE_P_2) },

   },
 
   /* PREFIX_VEX_0FDF */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FDF */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) },
+    { VEX_W_TABLE (VEX_W_0FDF_P_2) },

   },
 
   /* PREFIX_VEX_0FE0 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE0 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE0_P_2) },

   },
 
   /* PREFIX_VEX_0FE1 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE1 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE1_P_2) },

   },
 
   /* PREFIX_VEX_0FE2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE2_P_2) },

   },
 
   /* PREFIX_VEX_0FE3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE3_P_2) },

   },
 
   /* PREFIX_VEX_0FE4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE4_P_2) },

   },
 
   /* PREFIX_VEX_0FE5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE5_P_2) },

   },
 
   /* PREFIX_VEX_0FE6 */
   },
 
   /* PREFIX_VEX_0FE6 */


@@ -4229,56 +5282,56 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE8_P_2) },

   },
 
   /* PREFIX_VEX_0FE9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FE9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) },
+    { VEX_W_TABLE (VEX_W_0FE9_P_2) },

   },
 
   /* PREFIX_VEX_0FEA */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FEA */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) },
+    { VEX_W_TABLE (VEX_W_0FEA_P_2) },

   },
 
   /* PREFIX_VEX_0FEB */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FEB */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) },
+    { VEX_W_TABLE (VEX_W_0FEB_P_2) },

   },
 
   /* PREFIX_VEX_0FEC */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FEC */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) },
+    { VEX_W_TABLE (VEX_W_0FEC_P_2) },

   },
 
   /* PREFIX_VEX_0FED */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FED */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) },
+    { VEX_W_TABLE (VEX_W_0FED_P_2) },

   },
 
   /* PREFIX_VEX_0FEE */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FEE */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) },
+    { VEX_W_TABLE (VEX_W_0FEE_P_2) },

   },
 
   /* PREFIX_VEX_0FEF */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FEF */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) },
+    { VEX_W_TABLE (VEX_W_0FEF_P_2) },

   },
 
   /* PREFIX_VEX_0FF0 */
   },
 
   /* PREFIX_VEX_0FF0 */


@@ -4293,42 +5346,42 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF1_P_2) },

   },
 
   /* PREFIX_VEX_0FF2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF2 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF2_P_2) },

   },
 
   /* PREFIX_VEX_0FF3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF3 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF3_P_2) },

   },
 
   /* PREFIX_VEX_0FF4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF4 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF4_P_2) },

   },
 
   /* PREFIX_VEX_0FF5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF5_P_2) },

   },
 
   /* PREFIX_VEX_0FF6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF6 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF6_P_2) },

   },
 
   /* PREFIX_VEX_0FF7 */
   },
 
   /* PREFIX_VEX_0FF7 */


@@ -4342,133 +5395,133 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF8_P_2) },

   },
 
   /* PREFIX_VEX_0FF9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FF9 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF9_P_2) },

   },
 
   /* PREFIX_VEX_0FFA */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FFA */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) },
+    { VEX_W_TABLE (VEX_W_0FFA_P_2) },

   },
 
   /* PREFIX_VEX_0FFB */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FFB */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) },
+    { VEX_W_TABLE (VEX_W_0FFB_P_2) },

   },
 
   /* PREFIX_VEX_0FFC */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FFC */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) },
+    { VEX_W_TABLE (VEX_W_0FFC_P_2) },

   },
 
   /* PREFIX_VEX_0FFD */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FFD */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) },
+    { VEX_W_TABLE (VEX_W_0FFD_P_2) },

   },
 
   /* PREFIX_VEX_0FFE */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0FFE */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) },
+    { VEX_W_TABLE (VEX_W_0FFE_P_2) },

   },
 
   /* PREFIX_VEX_0F3800 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3800 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3800_P_2) },

   },
 
   /* PREFIX_VEX_0F3801 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3801 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3801_P_2) },

   },
 
   /* PREFIX_VEX_0F3802 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3802 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3802_P_2) },

   },
 
   /* PREFIX_VEX_0F3803 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3803 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3803_P_2) },

   },
 
   /* PREFIX_VEX_0F3804 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3804 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3804_P_2) },

   },
 
   /* PREFIX_VEX_0F3805 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3805 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3805_P_2) },

   },
 
   /* PREFIX_VEX_0F3806 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3806 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3806_P_2) },

   },
 
   /* PREFIX_VEX_0F3807 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3807 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3807_P_2) },

   },
 
   /* PREFIX_VEX_0F3808 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3808 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3808_P_2) },

   },
 
   /* PREFIX_VEX_0F3809 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3809 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3809_P_2) },

   },
 
   /* PREFIX_VEX_0F380A */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F380A */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) },
+    { VEX_W_TABLE (VEX_W_0F380A_P_2) },

   },
 
   /* PREFIX_VEX_0F380B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F380B */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F380B_P_2) },

   },
 
   /* PREFIX_VEX_0F380C */
   },
 
   /* PREFIX_VEX_0F380C */


@@ -4506,25 +5559,32 @@ static const struct dis386 prefix_table[][4] = {
     { "vcvtph2ps", { XM, EXxmmq } },
   },
 
     { "vcvtph2ps", { XM, EXxmmq } },
   },
 

-  /* PREFIX_VEX_0F3817 */
+  /* PREFIX_VEX_0F3816 */

   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+    { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },

   },
 
   },
 

-  /* PREFIX_VEX_0F3818 */
+  /* PREFIX_VEX_0F3817 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3818 */

   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) },
+    { VEX_W_TABLE (VEX_W_0F3818_P_2) },

   },
 
   /* PREFIX_VEX_0F3819 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3819 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) },
+    { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },

   },
 
   /* PREFIX_VEX_0F381A */
   },
 
   /* PREFIX_VEX_0F381A */


@@ -4538,77 +5598,77 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) },
+    { VEX_W_TABLE (VEX_W_0F381C_P_2) },

   },
 
   /* PREFIX_VEX_0F381D */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F381D */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) },
+    { VEX_W_TABLE (VEX_W_0F381D_P_2) },

   },
 
   /* PREFIX_VEX_0F381E */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F381E */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) },
+    { VEX_W_TABLE (VEX_W_0F381E_P_2) },

   },
 
   /* PREFIX_VEX_0F3820 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3820 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3820_P_2) },

   },
 
   /* PREFIX_VEX_0F3821 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3821 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3821_P_2) },

   },
 
   /* PREFIX_VEX_0F3822 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3822 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3822_P_2) },

   },
 
   /* PREFIX_VEX_0F3823 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3823 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3823_P_2) },

   },
 
   /* PREFIX_VEX_0F3824 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3824 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3824_P_2) },

   },
 
   /* PREFIX_VEX_0F3825 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3825 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3825_P_2) },

   },
 
   /* PREFIX_VEX_0F3828 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3828 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3828_P_2) },

   },
 
   /* PREFIX_VEX_0F3829 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3829 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3829_P_2) },

   },
 
   /* PREFIX_VEX_0F382A */
   },
 
   /* PREFIX_VEX_0F382A */


@@ -4622,7 +5682,7 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F382B_P_2) },

   },
 
   /* PREFIX_VEX_0F382C */
   },
 
   /* PREFIX_VEX_0F382C */


@@ -4657,112 +5717,119 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3830_P_2) },

   },
 
   /* PREFIX_VEX_0F3831 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3831 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3831_P_2) },

   },
 
   /* PREFIX_VEX_0F3832 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3832 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3832_P_2) },

   },
 
   /* PREFIX_VEX_0F3833 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3833 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3833_P_2) },

   },
 
   /* PREFIX_VEX_0F3834 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3834 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3834_P_2) },

   },
 
   /* PREFIX_VEX_0F3835 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3835 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3836 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },

   },
 
   /* PREFIX_VEX_0F3837 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3837 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3837_P_2) },

   },
 
   /* PREFIX_VEX_0F3838 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3838 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3838_P_2) },

   },
 
   /* PREFIX_VEX_0F3839 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3839 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3839_P_2) },

   },
 
   /* PREFIX_VEX_0F383A */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383A */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383A_P_2) },

   },
 
   /* PREFIX_VEX_0F383B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383B */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383B_P_2) },

   },
 
   /* PREFIX_VEX_0F383C */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383C */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383C_P_2) },

   },
 
   /* PREFIX_VEX_0F383D */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383D */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383D_P_2) },

   },
 
   /* PREFIX_VEX_0F383E */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383E */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383E_P_2) },

   },
 
   /* PREFIX_VEX_0F383F */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F383F */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) },
+    { VEX_W_TABLE (VEX_W_0F383F_P_2) },

   },
 
   /* PREFIX_VEX_0F3840 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3840 */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3840_P_2) },

   },
 
   /* PREFIX_VEX_0F3841 */
   },
 
   /* PREFIX_VEX_0F3841 */


@@ -4772,6 +5839,104 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
   },
 
     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
   },
 

+  /* PREFIX_VEX_0F3845 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpsrlv%LW", { XM, Vex, EXx } },
+  },
+
+  /* PREFIX_VEX_0F3846 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3846_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3847 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpsllv%LW", { XM, Vex, EXx } },
+  },
+
+  /* PREFIX_VEX_0F3858 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3858_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3859 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3859_P_2) },
+  },
+
+  /* PREFIX_VEX_0F385A */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
+  },
+
+  /* PREFIX_VEX_0F3878 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3878_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3879 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3879_P_2) },
+  },
+
+  /* PREFIX_VEX_0F388C */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
+  },
+
+  /* PREFIX_VEX_0F388E */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
+  },
+
+  /* PREFIX_VEX_0F3890 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
+  },
+
+  /* PREFIX_VEX_0F3891 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
+  },
+
+  /* PREFIX_VEX_0F3892 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
+  },
+
+  /* PREFIX_VEX_0F3893 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
+  },
+

   /* PREFIX_VEX_0F3896 */
   {
     { Bad_Opcode },
   /* PREFIX_VEX_0F3896 */
   {
     { Bad_Opcode },


@@ -5038,9 +6203,49 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
   },
 
     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
   },
 

+  /* PREFIX_VEX_0F38F5 */
+  {
+    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
+    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
+  },
+
+  /* PREFIX_VEX_0F38F6 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
+  },
+

   /* PREFIX_VEX_0F38F7 */
   {
     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
   /* PREFIX_VEX_0F38F7 */
   {
     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },

+    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
+    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
+    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
+  },
+
+  /* PREFIX_VEX_0F3A00 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A01 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A02 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A02_P_2) },

   },
 
   /* PREFIX_VEX_0F3A04 */
   },
 
   /* PREFIX_VEX_0F3A04 */


@@ -5110,14 +6315,14 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },

   },
 
   /* PREFIX_VEX_0F3A0F */
   {
     { Bad_Opcode },
     { Bad_Opcode },
   },
 
   /* PREFIX_VEX_0F3A0F */
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },

   },
 
   /* PREFIX_VEX_0F3A14 */
   },
 
   /* PREFIX_VEX_0F3A14 */


@@ -5190,6 +6395,48 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
   },
 
     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
   },
 

+  /* PREFIX_VEX_0F3A30 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A31 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A32 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A33 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A38 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
+  },
+
+  /* PREFIX_VEX_0F3A39 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
+  },
+

   /* PREFIX_VEX_0F3A40 */
   {
     { Bad_Opcode },
   /* PREFIX_VEX_0F3A40 */
   {
     { Bad_Opcode },


@@ -5208,7 +6455,7 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A42_P_2) },

   },
 
   /* PREFIX_VEX_0F3A44 */
   },
 
   /* PREFIX_VEX_0F3A44 */


@@ -5218,6 +6465,13 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
   },
 
     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
   },
 

+  /* PREFIX_VEX_0F3A46 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
+  },
+

   /* PREFIX_VEX_0F3A48 */
   {
     { Bad_Opcode },
   /* PREFIX_VEX_0F3A48 */
   {
     { Bad_Opcode },


@@ -5250,7 +6504,7 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
   {
     { Bad_Opcode },
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },

   },
 
   /* PREFIX_VEX_0F3A5C */
   },
 
   /* PREFIX_VEX_0F3A5C */


@@ -5429,6 +6683,18 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },

+
+  /* PREFIX_VEX_0F3AF0 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
+  },
+
+#define NEED_PREFIX_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_PREFIX_TABLE

 };
 
 static const struct dis386 x86_64_table[][2] = {
 };
 
 static const struct dis386 x86_64_table[][2] = {


@@ -5500,6 +6766,7 @@ static const struct dis386 x86_64_table[][2] = {
   /* X86_64_62 */
   {
     { MOD_TABLE (MOD_62_32BIT) },
   /* X86_64_62 */
   {
     { MOD_TABLE (MOD_62_32BIT) },

+    { EVEX_TABLE (EVEX_0F) },

   },
 
   /* X86_64_63 */
   },
 
   /* X86_64_63 */


@@ -5544,12 +6811,12 @@ static const struct dis386 x86_64_table[][2] = {
 
   /* X86_64_D4 */
   {
 
   /* X86_64_D4 */
   {

-    { "aam", { sIb } },
+    { "aam", { Ib } },

   },
 
   /* X86_64_D5 */
   {
   },
 
   /* X86_64_D5 */
   {

-    { "aad", { sIb } },
+    { "aad", { Ib } },

   },
 
   /* X86_64_EA */
   },
 
   /* X86_64_EA */


@@ -5733,7 +7000,7 @@ static const struct dis386 three_byte_table[][256] = {
     /* 80 */
     { PREFIX_TABLE (PREFIX_0F3880) },
     { PREFIX_TABLE (PREFIX_0F3881) },
     /* 80 */
     { PREFIX_TABLE (PREFIX_0F3880) },
     { PREFIX_TABLE (PREFIX_0F3881) },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F3882) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -5812,12 +7079,12 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* c8 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* c8 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38C8) },
+    { PREFIX_TABLE (PREFIX_0F38C9) },
+    { PREFIX_TABLE (PREFIX_0F38CA) },
+    { PREFIX_TABLE (PREFIX_0F38CB) },
+    { PREFIX_TABLE (PREFIX_0F38CC) },
+    { PREFIX_TABLE (PREFIX_0F38CD) },

     { Bad_Opcode },
     { Bad_Opcode },
     /* d0 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* d0 */


@@ -5863,7 +7130,7 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38F6) },

     { Bad_Opcode },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* f8 */
     { Bad_Opcode },


@@ -6107,7 +7374,7 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F3ACC) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -6482,7 +7749,7 @@ static const struct dis386 xop_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 10 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 10 */

-    { "bextr", { Gv, Ev, Iq } },
+    { Bad_Opcode },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -6693,10 +7960,10 @@ static const struct dis386 xop_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

-    { "vpcomb",        { XM, Vex128, EXx, Ib } },
-    { "vpcomw",        { XM, Vex128, EXx, Ib } },
-    { "vpcomd",        { XM, Vex128, EXx, Ib } },
-    { "vpcomq",        { XM, Vex128, EXx, Ib } },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },

     /* d0 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* d0 */
     { Bad_Opcode },
     { Bad_Opcode },


@@ -6729,10 +7996,10 @@ static const struct dis386 xop_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

-    { "vpcomub",       { XM, Vex128, EXx, Ib } },
-    { "vpcomuw",       { XM, Vex128, EXx, Ib } },
-    { "vpcomud",       { XM, Vex128, EXx, Ib } },
-    { "vpcomuq",       { XM, Vex128, EXx, Ib } },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },

     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7413,18 +8680,18 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     /* 40 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 40 */
     { Bad_Opcode },

+    { PREFIX_TABLE (PREFIX_VEX_0F41) },
+    { PREFIX_TABLE (PREFIX_VEX_0F42) },

     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F44) },
+    { PREFIX_TABLE (PREFIX_VEX_0F45) },
+    { PREFIX_TABLE (PREFIX_VEX_0F46) },
+    { PREFIX_TABLE (PREFIX_VEX_0F47) },

     /* 48 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 48 */
     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F4A) },
+    { PREFIX_TABLE (PREFIX_VEX_0F4B) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7502,17 +8769,17 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 90 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 90 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F90) },
+    { PREFIX_TABLE (PREFIX_VEX_0F91) },
+    { PREFIX_TABLE (PREFIX_VEX_0F92) },
+    { PREFIX_TABLE (PREFIX_VEX_0F93) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 98 */
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 98 */

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F98) },
+    { PREFIX_TABLE (PREFIX_VEX_0F99) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7655,7 +8922,7 @@ static const struct dis386 vex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
     { Bad_Opcode },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3816) },

     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
     /* 18 */
     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
     /* 18 */
     { PREFIX_TABLE (PREFIX_VEX_0F3818) },


@@ -7691,7 +8958,7 @@ static const struct dis386 vex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
     { PREFIX_TABLE (PREFIX_VEX_0F3835) },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3836) },

     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
     /* 38 */
     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
     /* 38 */
     { PREFIX_TABLE (PREFIX_VEX_0F3838) },


@@ -7708,9 +8975,9 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3845) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3846) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3847) },

     /* 48 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 48 */
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7730,9 +8997,9 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 58 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 58 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3858) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3859) },
+    { PREFIX_TABLE (PREFIX_VEX_0F385A) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7766,8 +9033,8 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 78 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 78 */

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3878) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3879) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -7788,15 +9055,15 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

+    { PREFIX_TABLE (PREFIX_VEX_0F388C) },

     { Bad_Opcode },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F388E) },

     { Bad_Opcode },
     /* 90 */
     { Bad_Opcode },
     /* 90 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3890) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3891) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3892) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3893) },

     { Bad_Opcode },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
     { Bad_Opcode },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3896) },


@@ -7906,8 +9173,8 @@ static const struct dis386 vex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
     { REG_TABLE (REG_VEX_0F38F3) },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
     { REG_TABLE (REG_VEX_0F38F3) },
     { Bad_Opcode },

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
+    { PREFIX_TABLE (PREFIX_VEX_0F38F6) },

     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
     /* f8 */
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
     /* f8 */
     { Bad_Opcode },


@@ -7922,9 +9189,9 @@ static const struct dis386 vex_table[][256] = {
   /* VEX_0F3A */
   {
     /* 00 */
   /* VEX_0F3A */
   {
     /* 00 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A02) },

     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },


@@ -7976,17 +9243,17 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 30 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* 30 */

-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A33) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 38 */
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 38 */

-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A39) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -8000,7 +9267,7 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
     { Bad_Opcode },
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
     { Bad_Opcode },

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3A46) },

     { Bad_Opcode },
     /* 48 */
     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
     { Bad_Opcode },
     /* 48 */
     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },


@@ -8192,7 +9459,7 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
     /* f0 */

-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },

     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },


@@ -8212,6 +9479,9 @@ static const struct dis386 vex_table[][256] = {
   },
 };
 
   },
 };
 

+#define NEED_OPCODE_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_OPCODE_TABLE

 static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F10_P_1 */
   {
 static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F10_P_1 */
   {


@@ -8337,745 +9607,346 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
   },
 

-  /* VEX_LEN_0F51_P_1 */
+  /* VEX_LEN_0F41_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F51_P_1) },
-    { VEX_W_TABLE (VEX_W_0F51_P_1) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0F51_P_3 */
+  /* VEX_LEN_0F41_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F51_P_3) },
-    { VEX_W_TABLE (VEX_W_0F51_P_3) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0F52_P_1 */
+  /* VEX_LEN_0F42_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F52_P_1) },
-    { VEX_W_TABLE (VEX_W_0F52_P_1) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0F53_P_1 */
+  /* VEX_LEN_0F42_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F53_P_1) },
-    { VEX_W_TABLE (VEX_W_0F53_P_1) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0F58_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F58_P_1) },
-    { VEX_W_TABLE (VEX_W_0F58_P_1) },
-  },
-
-  /* VEX_LEN_0F58_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F58_P_3) },
-    { VEX_W_TABLE (VEX_W_0F58_P_3) },
-  },
-
-  /* VEX_LEN_0F59_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F59_P_1) },
-    { VEX_W_TABLE (VEX_W_0F59_P_1) },
-  },
-
-  /* VEX_LEN_0F59_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F59_P_3) },
-    { VEX_W_TABLE (VEX_W_0F59_P_3) },
-  },
-
-  /* VEX_LEN_0F5A_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5A_P_1) },
-    { VEX_W_TABLE (VEX_W_0F5A_P_1) },
-  },
-
-  /* VEX_LEN_0F5A_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5A_P_3) },
-    { VEX_W_TABLE (VEX_W_0F5A_P_3) },
-  },
-
-  /* VEX_LEN_0F5C_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5C_P_1) },
-    { VEX_W_TABLE (VEX_W_0F5C_P_1) },
-  },
-
-  /* VEX_LEN_0F5C_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5C_P_3) },
-    { VEX_W_TABLE (VEX_W_0F5C_P_3) },
-  },
-
-  /* VEX_LEN_0F5D_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5D_P_1) },
-    { VEX_W_TABLE (VEX_W_0F5D_P_1) },
-  },
-
-  /* VEX_LEN_0F5D_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5D_P_3) },
-    { VEX_W_TABLE (VEX_W_0F5D_P_3) },
-  },
-
-  /* VEX_LEN_0F5E_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5E_P_1) },
-    { VEX_W_TABLE (VEX_W_0F5E_P_1) },
-  },
-
-  /* VEX_LEN_0F5E_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5E_P_3) },
-    { VEX_W_TABLE (VEX_W_0F5E_P_3) },
-  },
-
-  /* VEX_LEN_0F5F_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5F_P_1) },
-    { VEX_W_TABLE (VEX_W_0F5F_P_1) },
-  },
-
-  /* VEX_LEN_0F5F_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F5F_P_3) },
-    { VEX_W_TABLE (VEX_W_0F5F_P_3) },
-  },
-
-  /* VEX_LEN_0F60_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F60_P_2) },
-  },
-
-  /* VEX_LEN_0F61_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F61_P_2) },
-  },
-
-  /* VEX_LEN_0F62_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F62_P_2) },
-  },
-
-  /* VEX_LEN_0F63_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F63_P_2) },
-  },
-
-  /* VEX_LEN_0F64_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F64_P_2) },
-  },
-
-  /* VEX_LEN_0F65_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F65_P_2) },
-  },
-
-  /* VEX_LEN_0F66_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F66_P_2) },
-  },
-
-  /* VEX_LEN_0F67_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F67_P_2) },
-  },
-
-  /* VEX_LEN_0F68_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F68_P_2) },
-  },
-
-  /* VEX_LEN_0F69_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F69_P_2) },
-  },
-
-  /* VEX_LEN_0F6A_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F6A_P_2) },
-  },
-
-  /* VEX_LEN_0F6B_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F6B_P_2) },
-  },
-
-  /* VEX_LEN_0F6C_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F6C_P_2) },
-  },
-
-  /* VEX_LEN_0F6D_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F6D_P_2) },
-  },
-
-  /* VEX_LEN_0F6E_P_2 */
-  {
-    { "vmovK",         { XMScalar, Edq } },
-    { "vmovK",         { XMScalar, Edq } },
-  },
-
-  /* VEX_LEN_0F70_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F70_P_1) },
-  },
-
-  /* VEX_LEN_0F70_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F70_P_2) },
-  },
-
-  /* VEX_LEN_0F70_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0F70_P_3) },
-  },
-
-  /* VEX_LEN_0F71_R_2_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
-  },
-
-  /* VEX_LEN_0F71_R_4_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
-  },
-
-  /* VEX_LEN_0F71_R_6_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
-  },
-
-  /* VEX_LEN_0F72_R_2_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
-  },
-
-  /* VEX_LEN_0F72_R_4_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
-  },
-
-  /* VEX_LEN_0F72_R_6_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
-  },
-
-  /* VEX_LEN_0F73_R_2_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
-  },
-
-  /* VEX_LEN_0F73_R_3_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
-  },
-
-  /* VEX_LEN_0F73_R_6_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
-  },
-
-  /* VEX_LEN_0F73_R_7_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
-  },
-
-  /* VEX_LEN_0F74_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F74_P_2) },
-  },
-
-  /* VEX_LEN_0F75_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F75_P_2) },
-  },
-
-  /* VEX_LEN_0F76_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F76_P_2) },
-  },
-
-  /* VEX_LEN_0F7E_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
-    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
-  },
-
-  /* VEX_LEN_0F7E_P_2 */
-  {
-    { "vmovK",         { Edq, XMScalar } },
-    { "vmovK",         { Edq, XMScalar } },
-  },
-
-  /* VEX_LEN_0FAE_R_2_M_0 */
-  {
-    { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
-  },
-
-  /* VEX_LEN_0FAE_R_3_M_0 */
-  {
-    { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
-  },
-
-  /* VEX_LEN_0FC2_P_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0FC2_P_1) },
-    { VEX_W_TABLE (VEX_W_0FC2_P_1) },
-  },
-
-  /* VEX_LEN_0FC2_P_3 */
-  {
-    { VEX_W_TABLE (VEX_W_0FC2_P_3) },
-    { VEX_W_TABLE (VEX_W_0FC2_P_3) },
-  },
-
-  /* VEX_LEN_0FC4_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FC4_P_2) },
-  },
-
-  /* VEX_LEN_0FC5_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FC5_P_2) },
-  },
-
-  /* VEX_LEN_0FD1_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD1_P_2) },
-  },
-
-  /* VEX_LEN_0FD2_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD2_P_2) },
-  },
-
-  /* VEX_LEN_0FD3_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD3_P_2) },
-  },
-
-  /* VEX_LEN_0FD4_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD4_P_2) },
-  },
-
-  /* VEX_LEN_0FD5_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD5_P_2) },
-  },
-
-  /* VEX_LEN_0FD6_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
-    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
-  },
-
-  /* VEX_LEN_0FD7_P_2_M_1 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
-  },
-
-  /* VEX_LEN_0FD8_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD8_P_2) },
-  },
-
-  /* VEX_LEN_0FD9_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FD9_P_2) },
-  },
-
-  /* VEX_LEN_0FDA_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FDA_P_2) },
-  },
-
-  /* VEX_LEN_0FDB_P_2 */
+  /* VEX_LEN_0F44_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FDB_P_2) },
-  },
-
-  /* VEX_LEN_0FDC_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FDC_P_2) },
-  },
-
-  /* VEX_LEN_0FDD_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+    { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },

   },
   },

-
-  /* VEX_LEN_0FDE_P_2 */
+  /* VEX_LEN_0F44_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+    { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },

   },
   },

-
-  /* VEX_LEN_0FDF_P_2 */
+  /* VEX_LEN_0F45_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FDF_P_2) },
-  },
-
-  /* VEX_LEN_0FE0_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE0_P_2) },
-  },
-
-  /* VEX_LEN_0FE1_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE1_P_2) },
-  },
-
-  /* VEX_LEN_0FE2_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE2_P_2) },
-  },
-
-  /* VEX_LEN_0FE3_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE3_P_2) },
-  },
-
-  /* VEX_LEN_0FE4_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE4_P_2) },
-  },
-
-  /* VEX_LEN_0FE5_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE5_P_2) },
-  },
-
-  /* VEX_LEN_0FE8_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE8_P_2) },
-  },
-
-  /* VEX_LEN_0FE9_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FE9_P_2) },
-  },
-
-  /* VEX_LEN_0FEA_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FEA_P_2) },
-  },
-
-  /* VEX_LEN_0FEB_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FEB_P_2) },
-  },
-
-  /* VEX_LEN_0FEC_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FEC_P_2) },
-  },
-
-  /* VEX_LEN_0FED_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FED_P_2) },
-  },
-
-  /* VEX_LEN_0FEE_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FEE_P_2) },
-  },
-
-  /* VEX_LEN_0FEF_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FEF_P_2) },
-  },
-
-  /* VEX_LEN_0FF1_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF2_P_2 */
+  /* VEX_LEN_0F45_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF3_P_2 */
+  /* VEX_LEN_0F46_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF4_P_2 */
+  /* VEX_LEN_0F46_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF5_P_2 */
+  /* VEX_LEN_0F47_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF6_P_2 */
+  /* VEX_LEN_0F47_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF7_P_2 */
+  /* VEX_LEN_0F4A_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF8_P_2 */
+  /* VEX_LEN_0F4A_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FF9_P_2 */
+  /* VEX_LEN_0F4B_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },

   },
   },

-
-  /* VEX_LEN_0FFA_P_2 */
+  /* VEX_LEN_0F4B_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },

   },
 
   },
 

-  /* VEX_LEN_0FFB_P_2 */
+  /* VEX_LEN_0F51_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+    { VEX_W_TABLE (VEX_W_0F51_P_1) },
+    { VEX_W_TABLE (VEX_W_0F51_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0FFC_P_2 */
+  /* VEX_LEN_0F51_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+    { VEX_W_TABLE (VEX_W_0F51_P_3) },
+    { VEX_W_TABLE (VEX_W_0F51_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0FFD_P_2 */
+  /* VEX_LEN_0F52_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+    { VEX_W_TABLE (VEX_W_0F52_P_1) },
+    { VEX_W_TABLE (VEX_W_0F52_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0FFE_P_2 */
+  /* VEX_LEN_0F53_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+    { VEX_W_TABLE (VEX_W_0F53_P_1) },
+    { VEX_W_TABLE (VEX_W_0F53_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3800_P_2 */
+  /* VEX_LEN_0F58_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+    { VEX_W_TABLE (VEX_W_0F58_P_1) },
+    { VEX_W_TABLE (VEX_W_0F58_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3801_P_2 */
+  /* VEX_LEN_0F58_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+    { VEX_W_TABLE (VEX_W_0F58_P_3) },
+    { VEX_W_TABLE (VEX_W_0F58_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3802_P_2 */
+  /* VEX_LEN_0F59_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+    { VEX_W_TABLE (VEX_W_0F59_P_1) },
+    { VEX_W_TABLE (VEX_W_0F59_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3803_P_2 */
+  /* VEX_LEN_0F59_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+    { VEX_W_TABLE (VEX_W_0F59_P_3) },
+    { VEX_W_TABLE (VEX_W_0F59_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3804_P_2 */
+  /* VEX_LEN_0F5A_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5A_P_1) },
+    { VEX_W_TABLE (VEX_W_0F5A_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3805_P_2 */
+  /* VEX_LEN_0F5A_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5A_P_3) },
+    { VEX_W_TABLE (VEX_W_0F5A_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3806_P_2 */
+  /* VEX_LEN_0F5C_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5C_P_1) },
+    { VEX_W_TABLE (VEX_W_0F5C_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3807_P_2 */
+  /* VEX_LEN_0F5C_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5C_P_3) },
+    { VEX_W_TABLE (VEX_W_0F5C_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3808_P_2 */
+  /* VEX_LEN_0F5D_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5D_P_1) },
+    { VEX_W_TABLE (VEX_W_0F5D_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3809_P_2 */
+  /* VEX_LEN_0F5D_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5D_P_3) },
+    { VEX_W_TABLE (VEX_W_0F5D_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F380A_P_2 */
+  /* VEX_LEN_0F5E_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F380A_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5E_P_1) },
+    { VEX_W_TABLE (VEX_W_0F5E_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F380B_P_2 */
+  /* VEX_LEN_0F5E_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F380B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F5E_P_3) },
+    { VEX_W_TABLE (VEX_W_0F5E_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3819_P_2_M_0 */
+  /* VEX_LEN_0F5F_P_1 */

   {
   {

-    { Bad_Opcode },
-    { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) },
+    { VEX_W_TABLE (VEX_W_0F5F_P_1) },
+    { VEX_W_TABLE (VEX_W_0F5F_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F381A_P_2_M_0 */
+  /* VEX_LEN_0F5F_P_3 */

   {
   {

-    { Bad_Opcode },
-    { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
+    { VEX_W_TABLE (VEX_W_0F5F_P_3) },
+    { VEX_W_TABLE (VEX_W_0F5F_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F381C_P_2 */
+  /* VEX_LEN_0F6E_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F381C_P_2) },
+    { "vmovK",         { XMScalar, Edq } },
+    { "vmovK",         { XMScalar, Edq } },

   },
 
   },
 

-  /* VEX_LEN_0F381D_P_2 */
+  /* VEX_LEN_0F7E_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F381D_P_2) },
+    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+    { VEX_W_TABLE (VEX_W_0F7E_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F381E_P_2 */
+  /* VEX_LEN_0F7E_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F381E_P_2) },
+    { "vmovK",         { Edq, XMScalar } },
+    { "vmovK",         { Edq, XMScalar } },

   },
 
   },
 

-  /* VEX_LEN_0F3820_P_2 */
+  /* VEX_LEN_0F90_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3820_P_2) },
+    { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3821_P_2 */
+  /* VEX_LEN_0F90_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3821_P_2) },
+    { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3822_P_2 */
+  /* VEX_LEN_0F91_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3822_P_2) },
+    { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3823_P_2 */
+  /* VEX_LEN_0F91_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3823_P_2) },
+    { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3824_P_2 */
+  /* VEX_LEN_0F92_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3824_P_2) },
+    { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3825_P_2 */
+  /* VEX_LEN_0F92_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3825_P_2) },
+    { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3828_P_2 */
+  /* VEX_LEN_0F92_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3828_P_2) },
+    { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3829_P_2 */
+  /* VEX_LEN_0F93_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3829_P_2) },
+    { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F382A_P_2_M_0 */
+  /* VEX_LEN_0F93_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
+    { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F382B_P_2 */
+  /* VEX_LEN_0F93_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F382B_P_2) },
+    { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3830_P_2 */
+  /* VEX_LEN_0F98_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3830_P_2) },
+    { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3831_P_2 */
+  /* VEX_LEN_0F98_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3831_P_2) },
+    { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3832_P_2 */
+  /* VEX_LEN_0F99_P_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3832_P_2) },
+    { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3833_P_2 */
+  /* VEX_LEN_0F99_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3833_P_2) },
+    { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3834_P_2 */
+  /* VEX_LEN_0FAE_R_2_M_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3834_P_2) },
+    { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3835_P_2 */
+  /* VEX_LEN_0FAE_R_3_M_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+    { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3837_P_2 */
+  /* VEX_LEN_0FC2_P_1 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3837_P_2) },
+    { VEX_W_TABLE (VEX_W_0FC2_P_1) },
+    { VEX_W_TABLE (VEX_W_0FC2_P_1) },

   },
 
   },
 

-  /* VEX_LEN_0F3838_P_2 */
+  /* VEX_LEN_0FC2_P_3 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3838_P_2) },
+    { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+    { VEX_W_TABLE (VEX_W_0FC2_P_3) },

   },
 
   },
 

-  /* VEX_LEN_0F3839_P_2 */
+  /* VEX_LEN_0FC4_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3839_P_2) },
+    { VEX_W_TABLE (VEX_W_0FC4_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383A_P_2 */
+  /* VEX_LEN_0FC5_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383A_P_2) },
+    { VEX_W_TABLE (VEX_W_0FC5_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383B_P_2 */
+  /* VEX_LEN_0FD6_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383B_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+    { VEX_W_TABLE (VEX_W_0FD6_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383C_P_2 */
+  /* VEX_LEN_0FF7_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383C_P_2) },
+    { VEX_W_TABLE (VEX_W_0FF7_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383D_P_2 */
+  /* VEX_LEN_0F3816_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383D_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3816_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383E_P_2 */
+  /* VEX_LEN_0F3819_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383E_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3819_P_2) },

   },
 
   },
 

-  /* VEX_LEN_0F383F_P_2 */
+  /* VEX_LEN_0F381A_P_2_M_0 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F383F_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3840_P_2 */
+  /* VEX_LEN_0F3836_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3840_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3836_P_2) },

   },
 
   /* VEX_LEN_0F3841_P_2 */
   },
 
   /* VEX_LEN_0F3841_P_2 */


@@ -9083,6 +9954,12 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
   },
 

+  /* VEX_LEN_0F385A_P_2_M_0 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
+  },
+

   /* VEX_LEN_0F38DB_P_2 */
   {
     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
   /* VEX_LEN_0F38DB_P_2 */
   {
     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },


@@ -9128,11 +10005,58 @@ static const struct dis386 vex_len_table[][2] = {
     { "blsiS",         { VexGdq, Edq } },
   },
 
     { "blsiS",         { VexGdq, Edq } },
   },
 

+  /* VEX_LEN_0F38F5_P_0 */
+  {
+    { "bzhiS",         { Gdq, Edq, VexGdq } },
+  },
+
+  /* VEX_LEN_0F38F5_P_1 */
+  {
+    { "pextS",         { Gdq, VexGdq, Edq } },
+  },
+
+  /* VEX_LEN_0F38F5_P_3 */
+  {
+    { "pdepS",         { Gdq, VexGdq, Edq } },
+  },
+
+  /* VEX_LEN_0F38F6_P_3 */
+  {
+    { "mulxS",         { Gdq, VexGdq, Edq } },
+  },
+

   /* VEX_LEN_0F38F7_P_0 */
   {
     { "bextrS",                { Gdq, Edq, VexGdq } },
   },
 
   /* VEX_LEN_0F38F7_P_0 */
   {
     { "bextrS",                { Gdq, Edq, VexGdq } },
   },
 

+  /* VEX_LEN_0F38F7_P_1 */
+  {
+    { "sarxS",         { Gdq, Edq, VexGdq } },
+  },
+
+  /* VEX_LEN_0F38F7_P_2 */
+  {
+    { "shlxS",         { Gdq, Edq, VexGdq } },
+  },
+
+  /* VEX_LEN_0F38F7_P_3 */
+  {
+    { "shrxS",         { Gdq, Edq, VexGdq } },
+  },
+
+  /* VEX_LEN_0F3A00_P_2 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
+  },
+
+  /* VEX_LEN_0F3A01_P_2 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
+  },
+

   /* VEX_LEN_0F3A06_P_2 */
   {
     { Bad_Opcode },
   /* VEX_LEN_0F3A06_P_2 */
   {
     { Bad_Opcode },


@@ -9151,16 +10075,6 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
   },
 

-  /* VEX_LEN_0F3A0E_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
-  },
-
-  /* VEX_LEN_0F3A0F_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
-  },
-

   /* VEX_LEN_0F3A14_P_2 */
   {
     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
   /* VEX_LEN_0F3A14_P_2 */
   {
     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },


@@ -9208,14 +10122,41 @@ static const struct dis386 vex_len_table[][2] = {
     { "vpinsrK",       { XM, Vex128, Edq, Ib } },
   },
 
     { "vpinsrK",       { XM, Vex128, Edq, Ib } },
   },
 

-  /* VEX_LEN_0F3A41_P_2 */
+  /* VEX_LEN_0F3A30_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },

   },
 
   },
 

-  /* VEX_LEN_0F3A42_P_2 */
+  /* VEX_LEN_0F3A31_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
+    { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
+  },
+
+  /* VEX_LEN_0F3A32_P_2 */
+  {
+    { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
+  },
+
+  /* VEX_LEN_0F3A33_P_2 */
+  {
+    { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
+  },
+
+  /* VEX_LEN_0F3A38_P_2 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
+  },
+
+  /* VEX_LEN_0F3A39_P_2 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
+  },
+
+  /* VEX_LEN_0F3A41_P_2 */
+  {
+    { VEX_W_TABLE (VEX_W_0F3A41_P_2) },

   },
 
   /* VEX_LEN_0F3A44_P_2 */
   },
 
   /* VEX_LEN_0F3A44_P_2 */


@@ -9223,9 +10164,10 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
   },
 

-  /* VEX_LEN_0F3A4C_P_2 */
+  /* VEX_LEN_0F3A46_P_2 */

   {
   {

-    { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3A46_P_2) },

   },
 
   /* VEX_LEN_0F3A60_P_2 */
   },
 
   /* VEX_LEN_0F3A60_P_2 */


@@ -9293,6 +10235,51 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
   },
 
     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
   },
 

+  /* VEX_LEN_0F3AF0_P_3 */
+  {
+    { "rorxS",         { Gdq, Edq, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_CC */
+  {
+     { "vpcomb",       { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_CD */
+  {
+     { "vpcomw",       { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_CE */
+  {
+     { "vpcomd",       { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_CF */
+  {
+     { "vpcomq",       { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_EC */
+  {
+     { "vpcomub",      { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_ED */
+  {
+     { "vpcomuw",      { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_EE */
+  {
+     { "vpcomud",      { XM, Vex128, EXx, Ib } },
+  },
+
+  /* VEX_LEN_0FXOP_08_EF */
+  {
+     { "vpcomuq",      { XM, Vex128, EXx, Ib } },
+  },
+

   /* VEX_LEN_0FXOP_09_80 */
   {
     { "vfrczps",       { XM, EXxmm } },
   /* VEX_LEN_0FXOP_09_80 */
   {
     { "vfrczps",       { XM, EXxmm } },


@@ -9405,11 +10392,11 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F2E_P_0 */
   },
   {
     /* VEX_W_0F2E_P_0 */

-    { "vucomiss",      { XMScalar, EXdScalar } }, 
+    { "vucomiss",      { XMScalar, EXdScalar } },

   },
   {
     /* VEX_W_0F2E_P_2 */
   },
   {
     /* VEX_W_0F2E_P_2 */

-    { "vucomisd",      { XMScalar, EXqScalar } }, 
+    { "vucomisd",      { XMScalar, EXqScalar } },

   },
   {
     /* VEX_W_0F2F_P_0 */
   },
   {
     /* VEX_W_0F2F_P_0 */


@@ -9420,6 +10407,85 @@ static const struct dis386 vex_w_table[][2] = {
     { "vcomisd",       { XMScalar, EXqScalar } },
   },
   {
     { "vcomisd",       { XMScalar, EXqScalar } },
   },
   {

+    /* VEX_W_0F41_P_0_LEN_1 */
+    { "kandw",          { MaskG, MaskVex, MaskR } },
+    { "kandq",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F41_P_2_LEN_1 */
+    { "kandb",          { MaskG, MaskVex, MaskR } },
+    { "kandd",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F42_P_0_LEN_1 */
+    { "kandnw",         { MaskG, MaskVex, MaskR } },
+    { "kandnq",         { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F42_P_2_LEN_1 */
+    { "kandnb",         { MaskG, MaskVex, MaskR } },
+    { "kandnd",         { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F44_P_0_LEN_0 */
+    { "knotw",         { MaskG, MaskR } },
+    { "knotq",         { MaskG, MaskR } },
+  },
+  {
+    /* VEX_W_0F44_P_2_LEN_0 */
+    { "knotb",         { MaskG, MaskR } },
+    { "knotd",         { MaskG, MaskR } },
+  },
+  {
+    /* VEX_W_0F45_P_0_LEN_1 */
+    { "korw",           { MaskG, MaskVex, MaskR } },
+    { "korq",           { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F45_P_2_LEN_1 */
+    { "korb",           { MaskG, MaskVex, MaskR } },
+    { "kord",           { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F46_P_0_LEN_1 */
+    { "kxnorw",         { MaskG, MaskVex, MaskR } },
+    { "kxnorq",         { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F46_P_2_LEN_1 */
+    { "kxnorb",         { MaskG, MaskVex, MaskR } },
+    { "kxnord",         { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F47_P_0_LEN_1 */
+    { "kxorw",          { MaskG, MaskVex, MaskR } },
+    { "kxorq",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F47_P_2_LEN_1 */
+    { "kxorb",          { MaskG, MaskVex, MaskR } },
+    { "kxord",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F4A_P_0_LEN_1 */
+    { "kaddw",          { MaskG, MaskVex, MaskR } },
+    { "kaddq",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F4A_P_2_LEN_1 */
+    { "kaddb",          { MaskG, MaskVex, MaskR } },
+    { "kaddd",          { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F4B_P_0_LEN_1 */
+    { "kunpckwd",      { MaskG, MaskVex, MaskR } },
+    { "kunpckdq",      { MaskG, MaskVex, MaskR } },
+  },
+  {
+    /* VEX_W_0F4B_P_2_LEN_1 */
+    { "kunpckbw",      { MaskG, MaskVex, MaskR } },
+  },
+  {

     /* VEX_W_0F50_M_0 */
     { "vmovmskpX",     { Gdq, XS } },
   },
     /* VEX_W_0F50_M_0 */
     { "vmovmskpX",     { Gdq, XS } },
   },


@@ -9577,59 +10643,59 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F60_P_2  */
   },
   {
     /* VEX_W_0F60_P_2  */

-    { "vpunpcklbw",    { XM, Vex128, EXx } },
+    { "vpunpcklbw",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F61_P_2  */
   },
   {
     /* VEX_W_0F61_P_2  */

-    { "vpunpcklwd",    { XM, Vex128, EXx } },
+    { "vpunpcklwd",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F62_P_2  */
   },
   {
     /* VEX_W_0F62_P_2  */

-    { "vpunpckldq",    { XM, Vex128, EXx } },
+    { "vpunpckldq",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F63_P_2  */
   },
   {
     /* VEX_W_0F63_P_2  */

-    { "vpacksswb",     { XM, Vex128, EXx } },
+    { "vpacksswb",     { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F64_P_2  */
   },
   {
     /* VEX_W_0F64_P_2  */

-    { "vpcmpgtb",      { XM, Vex128, EXx } },
+    { "vpcmpgtb",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F65_P_2  */
   },
   {
     /* VEX_W_0F65_P_2  */

-    { "vpcmpgtw",      { XM, Vex128, EXx } },
+    { "vpcmpgtw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F66_P_2  */
   },
   {
     /* VEX_W_0F66_P_2  */

-    { "vpcmpgtd",      { XM, Vex128, EXx } },
+    { "vpcmpgtd",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F67_P_2  */
   },
   {
     /* VEX_W_0F67_P_2  */

-    { "vpackuswb",     { XM, Vex128, EXx } },
+    { "vpackuswb",     { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F68_P_2  */
   },
   {
     /* VEX_W_0F68_P_2  */

-    { "vpunpckhbw",    { XM, Vex128, EXx } },
+    { "vpunpckhbw",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F69_P_2  */
   },
   {
     /* VEX_W_0F69_P_2  */

-    { "vpunpckhwd",    { XM, Vex128, EXx } },
+    { "vpunpckhwd",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F6A_P_2  */
   },
   {
     /* VEX_W_0F6A_P_2  */

-    { "vpunpckhdq",    { XM, Vex128, EXx } },
+    { "vpunpckhdq",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F6B_P_2  */
   },
   {
     /* VEX_W_0F6B_P_2  */

-    { "vpackssdw",     { XM, Vex128, EXx } },
+    { "vpackssdw",     { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F6C_P_2  */
   },
   {
     /* VEX_W_0F6C_P_2  */

-    { "vpunpcklqdq",   { XM, Vex128, EXx } },
+    { "vpunpcklqdq",   { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F6D_P_2  */
   },
   {
     /* VEX_W_0F6D_P_2  */

-    { "vpunpckhqdq",   { XM, Vex128, EXx } },
+    { "vpunpckhqdq",   { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F6F_P_1  */
   },
   {
     /* VEX_W_0F6F_P_1  */


@@ -9653,55 +10719,55 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F71_R_2_P_2  */
   },
   {
     /* VEX_W_0F71_R_2_P_2  */

-    { "vpsrlw",                { Vex128, XS, Ib } },
+    { "vpsrlw",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F71_R_4_P_2  */
   },
   {
     /* VEX_W_0F71_R_4_P_2  */

-    { "vpsraw",                { Vex128, XS, Ib } },
+    { "vpsraw",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F71_R_6_P_2  */
   },
   {
     /* VEX_W_0F71_R_6_P_2  */

-    { "vpsllw",                { Vex128, XS, Ib } },
+    { "vpsllw",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F72_R_2_P_2  */
   },
   {
     /* VEX_W_0F72_R_2_P_2  */

-    { "vpsrld",                { Vex128, XS, Ib } },
+    { "vpsrld",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F72_R_4_P_2  */
   },
   {
     /* VEX_W_0F72_R_4_P_2  */

-    { "vpsrad",                { Vex128, XS, Ib } },
+    { "vpsrad",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F72_R_6_P_2  */
   },
   {
     /* VEX_W_0F72_R_6_P_2  */

-    { "vpslld",                { Vex128, XS, Ib } },
+    { "vpslld",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F73_R_2_P_2  */
   },
   {
     /* VEX_W_0F73_R_2_P_2  */

-    { "vpsrlq",                { Vex128, XS, Ib } },
+    { "vpsrlq",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F73_R_3_P_2  */
   },
   {
     /* VEX_W_0F73_R_3_P_2  */

-    { "vpsrldq",       { Vex128, XS, Ib } },
+    { "vpsrldq",       { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F73_R_6_P_2  */
   },
   {
     /* VEX_W_0F73_R_6_P_2  */

-    { "vpsllq",                { Vex128, XS, Ib } },
+    { "vpsllq",                { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F73_R_7_P_2  */
   },
   {
     /* VEX_W_0F73_R_7_P_2  */

-    { "vpslldq",       { Vex128, XS, Ib } },
+    { "vpslldq",       { Vex, XS, Ib } },

   },
   {
     /* VEX_W_0F74_P_2 */
   },
   {
     /* VEX_W_0F74_P_2 */

-    { "vpcmpeqb",      { XM, Vex128, EXx } },
+    { "vpcmpeqb",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F75_P_2 */
   },
   {
     /* VEX_W_0F75_P_2 */

-    { "vpcmpeqw",      { XM, Vex128, EXx } },
+    { "vpcmpeqw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F76_P_2 */
   },
   {
     /* VEX_W_0F76_P_2 */

-    { "vpcmpeqd",      { XM, Vex128, EXx } },
+    { "vpcmpeqd",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F77_P_0 */
   },
   {
     /* VEX_W_0F77_P_0 */


@@ -9736,6 +10802,72 @@ static const struct dis386 vex_w_table[][2] = {
     { "vmovdqa",       { EXxS, XM } },
   },
   {
     { "vmovdqa",       { EXxS, XM } },
   },
   {

+    /* VEX_W_0F90_P_0_LEN_0 */
+    { "kmovw",         { MaskG, MaskE } },
+    { "kmovq",         { MaskG, MaskE } },
+  },
+  {
+    /* VEX_W_0F90_P_2_LEN_0 */
+    { "kmovb",         { MaskG, MaskBDE } },
+    { "kmovd",         { MaskG, MaskBDE } },
+  },
+  {
+    /* VEX_W_0F91_P_0_LEN_0 */
+    { "kmovw",         { Ew, MaskG } },
+    { "kmovq",         { Eq, MaskG } },
+  },
+  {
+    /* VEX_W_0F91_P_2_LEN_0 */
+    { "kmovb",         { Eb, MaskG } },
+    { "kmovd",         { Ed, MaskG } },
+  },
+  {
+    /* VEX_W_0F92_P_0_LEN_0 */
+    { "kmovw",         { MaskG, Rdq } },
+  },
+  {
+    /* VEX_W_0F92_P_2_LEN_0 */
+    { "kmovb",         { MaskG, Rdq } },
+  },
+  {
+    /* VEX_W_0F92_P_3_LEN_0 */
+    { "kmovd",         { MaskG, Rdq } },
+    { "kmovq",         { MaskG, Rdq } },
+  },
+  {
+    /* VEX_W_0F93_P_0_LEN_0 */
+    { "kmovw",         { Gdq, MaskR } },
+  },
+  {
+    /* VEX_W_0F93_P_2_LEN_0 */
+    { "kmovb",         { Gdq, MaskR } },
+  },
+  {
+    /* VEX_W_0F93_P_3_LEN_0 */
+    { "kmovd",         { Gdq, MaskR } },
+    { "kmovq",         { Gdq, MaskR } },
+  },
+  {
+    /* VEX_W_0F98_P_0_LEN_0 */
+    { "kortestw",      { MaskG, MaskR } },
+    { "kortestq",      { MaskG, MaskR } },
+  },
+  {
+    /* VEX_W_0F98_P_2_LEN_0 */
+    { "kortestb",      { MaskG, MaskR } },
+    { "kortestd",      { MaskG, MaskR } },
+  },
+  {
+    /* VEX_W_0F99_P_0_LEN_0 */
+    { "ktestw",        { MaskG, MaskR } },
+    { "ktestq",        { MaskG, MaskR } },
+  },
+  {
+    /* VEX_W_0F99_P_2_LEN_0 */
+    { "ktestb",        { MaskG, MaskR } },
+    { "ktestd",        { MaskG, MaskR } },
+  },
+  {

     /* VEX_W_0FAE_R_2_M_0 */
     { "vldmxcsr",      { Md } },
   },
     /* VEX_W_0FAE_R_2_M_0 */
     { "vldmxcsr",      { Md } },
   },


@@ -9777,23 +10909,23 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0FD1_P_2 */
   },
   {
     /* VEX_W_0FD1_P_2 */

-    { "vpsrlw",                { XM, Vex128, EXx } },
+    { "vpsrlw",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FD2_P_2 */
   },
   {
     /* VEX_W_0FD2_P_2 */

-    { "vpsrld",                { XM, Vex128, EXx } },
+    { "vpsrld",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FD3_P_2 */
   },
   {
     /* VEX_W_0FD3_P_2 */

-    { "vpsrlq",                { XM, Vex128, EXx } },
+    { "vpsrlq",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FD4_P_2 */
   },
   {
     /* VEX_W_0FD4_P_2 */

-    { "vpaddq",                { XM, Vex128, EXx } },
+    { "vpaddq",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FD5_P_2 */
   },
   {
     /* VEX_W_0FD5_P_2 */

-    { "vpmullw",       { XM, Vex128, EXx } },
+    { "vpmullw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FD6_P_2 */
   },
   {
     /* VEX_W_0FD6_P_2 */


@@ -9805,59 +10937,59 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0FD8_P_2 */
   },
   {
     /* VEX_W_0FD8_P_2 */

-    { "vpsubusb",      { XM, Vex128, EXx } },
+    { "vpsubusb",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FD9_P_2 */
   },
   {
     /* VEX_W_0FD9_P_2 */

-    { "vpsubusw",      { XM, Vex128, EXx } },
+    { "vpsubusw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDA_P_2 */
   },
   {
     /* VEX_W_0FDA_P_2 */

-    { "vpminub",       { XM, Vex128, EXx } },
+    { "vpminub",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDB_P_2 */
   },
   {
     /* VEX_W_0FDB_P_2 */

-    { "vpand",         { XM, Vex128, EXx } },
+    { "vpand",         { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDC_P_2 */
   },
   {
     /* VEX_W_0FDC_P_2 */

-    { "vpaddusb",      { XM, Vex128, EXx } },
+    { "vpaddusb",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDD_P_2 */
   },
   {
     /* VEX_W_0FDD_P_2 */

-    { "vpaddusw",      { XM, Vex128, EXx } },
+    { "vpaddusw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDE_P_2 */
   },
   {
     /* VEX_W_0FDE_P_2 */

-    { "vpmaxub",       { XM, Vex128, EXx } },
+    { "vpmaxub",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FDF_P_2 */
   },
   {
     /* VEX_W_0FDF_P_2 */

-    { "vpandn",                { XM, Vex128, EXx } },
+    { "vpandn",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE0_P_2  */
   },
   {
     /* VEX_W_0FE0_P_2  */

-    { "vpavgb",                { XM, Vex128, EXx } },
+    { "vpavgb",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE1_P_2  */
   },
   {
     /* VEX_W_0FE1_P_2  */

-    { "vpsraw",                { XM, Vex128, EXx } },
+    { "vpsraw",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FE2_P_2  */
   },
   {
     /* VEX_W_0FE2_P_2  */

-    { "vpsrad",                { XM, Vex128, EXx } },
+    { "vpsrad",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FE3_P_2  */
   },
   {
     /* VEX_W_0FE3_P_2  */

-    { "vpavgw",                { XM, Vex128, EXx } },
+    { "vpavgw",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE4_P_2  */
   },
   {
     /* VEX_W_0FE4_P_2  */

-    { "vpmulhuw",      { XM, Vex128, EXx } },
+    { "vpmulhuw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE5_P_2  */
   },
   {
     /* VEX_W_0FE5_P_2  */

-    { "vpmulhw",       { XM, Vex128, EXx } },
+    { "vpmulhw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE6_P_1  */
   },
   {
     /* VEX_W_0FE6_P_1  */


@@ -9877,35 +11009,35 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0FE8_P_2  */
   },
   {
     /* VEX_W_0FE8_P_2  */

-    { "vpsubsb",       { XM, Vex128, EXx } },
+    { "vpsubsb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FE9_P_2  */
   },
   {
     /* VEX_W_0FE9_P_2  */

-    { "vpsubsw",       { XM, Vex128, EXx } },
+    { "vpsubsw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FEA_P_2  */
   },
   {
     /* VEX_W_0FEA_P_2  */

-    { "vpminsw",       { XM, Vex128, EXx } },
+    { "vpminsw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FEB_P_2  */
   },
   {
     /* VEX_W_0FEB_P_2  */

-    { "vpor",          { XM, Vex128, EXx } },
+    { "vpor",          { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FEC_P_2  */
   },
   {
     /* VEX_W_0FEC_P_2  */

-    { "vpaddsb",       { XM, Vex128, EXx } },
+    { "vpaddsb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FED_P_2  */
   },
   {
     /* VEX_W_0FED_P_2  */

-    { "vpaddsw",       { XM, Vex128, EXx } },
+    { "vpaddsw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FEE_P_2  */
   },
   {
     /* VEX_W_0FEE_P_2  */

-    { "vpmaxsw",       { XM, Vex128, EXx } },
+    { "vpmaxsw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FEF_P_2  */
   },
   {
     /* VEX_W_0FEF_P_2  */

-    { "vpxor",         { XM, Vex128, EXx } },
+    { "vpxor",         { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FF0_P_3_M_0 */
   },
   {
     /* VEX_W_0FF0_P_3_M_0 */


@@ -9913,27 +11045,27 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0FF1_P_2 */
   },
   {
     /* VEX_W_0FF1_P_2 */

-    { "vpsllw",                { XM, Vex128, EXx } },
+    { "vpsllw",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FF2_P_2 */
   },
   {
     /* VEX_W_0FF2_P_2 */

-    { "vpslld",                { XM, Vex128, EXx } },
+    { "vpslld",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FF3_P_2 */
   },
   {
     /* VEX_W_0FF3_P_2 */

-    { "vpsllq",                { XM, Vex128, EXx } },
+    { "vpsllq",                { XM, Vex, EXxmm } },

   },
   {
     /* VEX_W_0FF4_P_2 */
   },
   {
     /* VEX_W_0FF4_P_2 */

-    { "vpmuludq",      { XM, Vex128, EXx } },
+    { "vpmuludq",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FF5_P_2 */
   },
   {
     /* VEX_W_0FF5_P_2 */

-    { "vpmaddwd",      { XM, Vex128, EXx } },
+    { "vpmaddwd",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FF6_P_2 */
   },
   {
     /* VEX_W_0FF6_P_2 */

-    { "vpsadbw",       { XM, Vex128, EXx } },
+    { "vpsadbw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FF7_P_2 */
   },
   {
     /* VEX_W_0FF7_P_2 */


@@ -9941,79 +11073,79 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0FF8_P_2 */
   },
   {
     /* VEX_W_0FF8_P_2 */

-    { "vpsubb",                { XM, Vex128, EXx } },
+    { "vpsubb",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FF9_P_2 */
   },
   {
     /* VEX_W_0FF9_P_2 */

-    { "vpsubw",                { XM, Vex128, EXx } },
+    { "vpsubw",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FFA_P_2 */
   },
   {
     /* VEX_W_0FFA_P_2 */

-    { "vpsubd",                { XM, Vex128, EXx } },
+    { "vpsubd",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FFB_P_2 */
   },
   {
     /* VEX_W_0FFB_P_2 */

-    { "vpsubq",                { XM, Vex128, EXx } },
+    { "vpsubq",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FFC_P_2 */
   },
   {
     /* VEX_W_0FFC_P_2 */

-    { "vpaddb",                { XM, Vex128, EXx } },
+    { "vpaddb",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FFD_P_2 */
   },
   {
     /* VEX_W_0FFD_P_2 */

-    { "vpaddw",                { XM, Vex128, EXx } },
+    { "vpaddw",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0FFE_P_2 */
   },
   {
     /* VEX_W_0FFE_P_2 */

-    { "vpaddd",                { XM, Vex128, EXx } },
+    { "vpaddd",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3800_P_2  */
   },
   {
     /* VEX_W_0F3800_P_2  */

-    { "vpshufb",       { XM, Vex128, EXx } },
+    { "vpshufb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3801_P_2  */
   },
   {
     /* VEX_W_0F3801_P_2  */

-    { "vphaddw",       { XM, Vex128, EXx } },
+    { "vphaddw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3802_P_2  */
   },
   {
     /* VEX_W_0F3802_P_2  */

-    { "vphaddd",       { XM, Vex128, EXx } },
+    { "vphaddd",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3803_P_2  */
   },
   {
     /* VEX_W_0F3803_P_2  */

-    { "vphaddsw",      { XM, Vex128, EXx } },
+    { "vphaddsw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3804_P_2  */
   },
   {
     /* VEX_W_0F3804_P_2  */

-    { "vpmaddubsw",    { XM, Vex128, EXx } },
+    { "vpmaddubsw",    { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3805_P_2  */
   },
   {
     /* VEX_W_0F3805_P_2  */

-    { "vphsubw",       { XM, Vex128, EXx } },
+    { "vphsubw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3806_P_2  */
   },
   {
     /* VEX_W_0F3806_P_2  */

-    { "vphsubd",       { XM, Vex128, EXx } },
+    { "vphsubd",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3807_P_2  */
   },
   {
     /* VEX_W_0F3807_P_2  */

-    { "vphsubsw",      { XM, Vex128, EXx } },
+    { "vphsubsw",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3808_P_2  */
   },
   {
     /* VEX_W_0F3808_P_2  */

-    { "vpsignb",       { XM, Vex128, EXx } },
+    { "vpsignb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3809_P_2  */
   },
   {
     /* VEX_W_0F3809_P_2  */

-    { "vpsignw",       { XM, Vex128, EXx } },
+    { "vpsignw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F380A_P_2  */
   },
   {
     /* VEX_W_0F380A_P_2  */

-    { "vpsignd",       { XM, Vex128, EXx } },
+    { "vpsignd",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F380B_P_2  */
   },
   {
     /* VEX_W_0F380B_P_2  */

-    { "vpmulhrsw",     { XM, Vex128, EXx } },
+    { "vpmulhrsw",     { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F380C_P_2  */
   },
   {
     /* VEX_W_0F380C_P_2  */


@@ -10032,16 +11164,20 @@ static const struct dis386 vex_w_table[][2] = {
     { "vtestpd",       { XM, EXx } },
   },
   {
     { "vtestpd",       { XM, EXx } },
   },
   {

+    /* VEX_W_0F3816_P_2  */
+    { "vpermps",       { XM, Vex, EXx } },
+  },
+  {

     /* VEX_W_0F3817_P_2 */
     { "vptest",                { XM, EXx } },
   },
   {
     /* VEX_W_0F3817_P_2 */
     { "vptest",                { XM, EXx } },
   },
   {

-    /* VEX_W_0F3818_P_2_M_0 */
-    { "vbroadcastss",  { XM, Md } },
+    /* VEX_W_0F3818_P_2 */
+    { "vbroadcastss",  { XM, EXxmm_md } },

   },
   {
   },
   {

-    /* VEX_W_0F3819_P_2_M_0 */
-    { "vbroadcastsd",  { XM, Mq } },
+    /* VEX_W_0F3819_P_2 */
+    { "vbroadcastsd",  { XM, EXxmm_mq } },

   },
   {
     /* VEX_W_0F381A_P_2_M_0 */
   },
   {
     /* VEX_W_0F381A_P_2_M_0 */


@@ -10061,35 +11197,35 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3820_P_2 */
   },
   {
     /* VEX_W_0F3820_P_2 */

-    { "vpmovsxbw",     { XM, EXq } },
+    { "vpmovsxbw",     { XM, EXxmmq } },

   },
   {
     /* VEX_W_0F3821_P_2 */
   },
   {
     /* VEX_W_0F3821_P_2 */

-    { "vpmovsxbd",     { XM, EXd } },
+    { "vpmovsxbd",     { XM, EXxmmqd } },

   },
   {
     /* VEX_W_0F3822_P_2 */
   },
   {
     /* VEX_W_0F3822_P_2 */

-    { "vpmovsxbq",     { XM, EXw } },
+    { "vpmovsxbq",     { XM, EXxmmdw } },

   },
   {
     /* VEX_W_0F3823_P_2 */
   },
   {
     /* VEX_W_0F3823_P_2 */

-    { "vpmovsxwd",     { XM, EXq } },
+    { "vpmovsxwd",     { XM, EXxmmq } },

   },
   {
     /* VEX_W_0F3824_P_2 */
   },
   {
     /* VEX_W_0F3824_P_2 */

-    { "vpmovsxwq",     { XM, EXd } },
+    { "vpmovsxwq",     { XM, EXxmmqd } },

   },
   {
     /* VEX_W_0F3825_P_2 */
   },
   {
     /* VEX_W_0F3825_P_2 */

-    { "vpmovsxdq",     { XM, EXq } },
+    { "vpmovsxdq",     { XM, EXxmmq } },

   },
   {
     /* VEX_W_0F3828_P_2 */
   },
   {
     /* VEX_W_0F3828_P_2 */

-    { "vpmuldq",       { XM, Vex128, EXx } },
+    { "vpmuldq",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3829_P_2 */
   },
   {
     /* VEX_W_0F3829_P_2 */

-    { "vpcmpeqq",      { XM, Vex128, EXx } },
+    { "vpcmpeqq",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F382A_P_2_M_0 */
   },
   {
     /* VEX_W_0F382A_P_2_M_0 */


@@ -10097,7 +11233,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F382B_P_2 */
   },
   {
     /* VEX_W_0F382B_P_2 */

-    { "vpackusdw",     { XM, Vex128, EXx } },
+    { "vpackusdw",     { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F382C_P_2_M_0 */
   },
   {
     /* VEX_W_0F382C_P_2_M_0 */


@@ -10117,73 +11253,101 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3830_P_2 */
   },
   {
     /* VEX_W_0F3830_P_2 */

-    { "vpmovzxbw",     { XM, EXq } },
+    { "vpmovzxbw",     { XM, EXxmmq } },

   },
   {
     /* VEX_W_0F3831_P_2 */
   },
   {
     /* VEX_W_0F3831_P_2 */

-    { "vpmovzxbd",     { XM, EXd } },
+    { "vpmovzxbd",     { XM, EXxmmqd } },

   },
   {
     /* VEX_W_0F3832_P_2 */
   },
   {
     /* VEX_W_0F3832_P_2 */

-    { "vpmovzxbq",     { XM, EXw } },
+    { "vpmovzxbq",     { XM, EXxmmdw } },

   },
   {
     /* VEX_W_0F3833_P_2 */
   },
   {
     /* VEX_W_0F3833_P_2 */

-    { "vpmovzxwd",     { XM, EXq } },
+    { "vpmovzxwd",     { XM, EXxmmq } },

   },
   {
     /* VEX_W_0F3834_P_2 */
   },
   {
     /* VEX_W_0F3834_P_2 */

-    { "vpmovzxwq",     { XM, EXd } },
+    { "vpmovzxwq",     { XM, EXxmmqd } },

   },
   {
     /* VEX_W_0F3835_P_2 */
   },
   {
     /* VEX_W_0F3835_P_2 */

-    { "vpmovzxdq",     { XM, EXq } },
+    { "vpmovzxdq",     { XM, EXxmmq } },
+  },
+  {
+    /* VEX_W_0F3836_P_2  */
+    { "vpermd",                { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3837_P_2 */
   },
   {
     /* VEX_W_0F3837_P_2 */

-    { "vpcmpgtq",      { XM, Vex128, EXx } },
+    { "vpcmpgtq",      { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3838_P_2 */
   },
   {
     /* VEX_W_0F3838_P_2 */

-    { "vpminsb",       { XM, Vex128, EXx } },
+    { "vpminsb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3839_P_2 */
   },
   {
     /* VEX_W_0F3839_P_2 */

-    { "vpminsd",       { XM, Vex128, EXx } },
+    { "vpminsd",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383A_P_2 */
   },
   {
     /* VEX_W_0F383A_P_2 */

-    { "vpminuw",       { XM, Vex128, EXx } },
+    { "vpminuw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383B_P_2 */
   },
   {
     /* VEX_W_0F383B_P_2 */

-    { "vpminud",       { XM, Vex128, EXx } },
+    { "vpminud",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383C_P_2 */
   },
   {
     /* VEX_W_0F383C_P_2 */

-    { "vpmaxsb",       { XM, Vex128, EXx } },
+    { "vpmaxsb",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383D_P_2 */
   },
   {
     /* VEX_W_0F383D_P_2 */

-    { "vpmaxsd",       { XM, Vex128, EXx } },
+    { "vpmaxsd",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383E_P_2 */
   },
   {
     /* VEX_W_0F383E_P_2 */

-    { "vpmaxuw",       { XM, Vex128, EXx } },
+    { "vpmaxuw",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F383F_P_2 */
   },
   {
     /* VEX_W_0F383F_P_2 */

-    { "vpmaxud",       { XM, Vex128, EXx } },
+    { "vpmaxud",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3840_P_2 */
   },
   {
     /* VEX_W_0F3840_P_2 */

-    { "vpmulld",       { XM, Vex128, EXx } },
+    { "vpmulld",       { XM, Vex, EXx } },

   },
   {
     /* VEX_W_0F3841_P_2 */
     { "vphminposuw",   { XM, EXx } },
   },
   {
   },
   {
     /* VEX_W_0F3841_P_2 */
     { "vphminposuw",   { XM, EXx } },
   },
   {

+    /* VEX_W_0F3846_P_2 */
+    { "vpsravd",       { XM, Vex, EXx } },
+  },
+  {
+    /* VEX_W_0F3858_P_2 */
+    { "vpbroadcastd", { XM, EXxmm_md } },
+  },
+  {
+    /* VEX_W_0F3859_P_2 */
+    { "vpbroadcastq",  { XM, EXxmm_mq } },
+  },
+  {
+    /* VEX_W_0F385A_P_2_M_0 */
+    { "vbroadcasti128", { XM, Mxmm } },
+  },
+  {
+    /* VEX_W_0F3878_P_2 */
+    { "vpbroadcastb",  { XM, EXxmm_mb } },
+  },
+  {
+    /* VEX_W_0F3879_P_2 */
+    { "vpbroadcastw",  { XM, EXxmm_mw } },
+  },
+  {

     /* VEX_W_0F38DB_P_2 */
     { "vaesimc",       { XM, EXx } },
   },
     /* VEX_W_0F38DB_P_2 */
     { "vaesimc",       { XM, EXx } },
   },


@@ -10204,6 +11368,20 @@ static const struct dis386 vex_w_table[][2] = {
     { "vaesdeclast",   { XM, Vex128, EXx } },
   },
   {
     { "vaesdeclast",   { XM, Vex128, EXx } },
   },
   {

+    /* VEX_W_0F3A00_P_2 */
+    { Bad_Opcode },
+    { "vpermq",                { XM, EXx, Ib } },
+  },
+  {
+    /* VEX_W_0F3A01_P_2 */
+    { Bad_Opcode },
+    { "vpermpd",       { XM, EXx, Ib } },
+  },
+  {
+    /* VEX_W_0F3A02_P_2 */
+    { "vpblendd",      { XM, Vex, EXx, Ib } },
+  },
+  {

     /* VEX_W_0F3A04_P_2 */
     { "vpermilps",     { XM, EXx, Ib } },
   },
     /* VEX_W_0F3A04_P_2 */
     { "vpermilps",     { XM, EXx, Ib } },
   },


@@ -10241,11 +11419,11 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A0E_P_2 */
   },
   {
     /* VEX_W_0F3A0E_P_2 */

-    { "vpblendw",      { XM, Vex128, EXx, Ib } },
+    { "vpblendw",      { XM, Vex, EXx, Ib } },

   },
   {
     /* VEX_W_0F3A0F_P_2 */
   },
   {
     /* VEX_W_0F3A0F_P_2 */

-    { "vpalignr",      { XM, Vex128, EXx, Ib } },
+    { "vpalignr",      { XM, Vex, EXx, Ib } },

   },
   {
     /* VEX_W_0F3A14_P_2 */
   },
   {
     /* VEX_W_0F3A14_P_2 */


@@ -10272,6 +11450,34 @@ static const struct dis386 vex_w_table[][2] = {
     { "vinsertps",     { XM, Vex128, EXd, Ib } },
   },
   {
     { "vinsertps",     { XM, Vex128, EXd, Ib } },
   },
   {

+    /* VEX_W_0F3A30_P_2_LEN_0 */
+    { "kshiftrb",      { MaskG, MaskR, Ib } },
+    { "kshiftrw",      { MaskG, MaskR, Ib } },
+  },
+  {
+    /* VEX_W_0F3A31_P_2_LEN_0 */
+    { "kshiftrd",      { MaskG, MaskR, Ib } },
+    { "kshiftrq",      { MaskG, MaskR, Ib } },
+  },
+  {
+    /* VEX_W_0F3A32_P_2_LEN_0 */
+    { "kshiftlb",      { MaskG, MaskR, Ib } },
+    { "kshiftlw",      { MaskG, MaskR, Ib } },
+  },
+  {
+    /* VEX_W_0F3A33_P_2_LEN_0 */
+    { "kshiftld",      { MaskG, MaskR, Ib } },
+    { "kshiftlq",      { MaskG, MaskR, Ib } },
+  },
+  {
+    /* VEX_W_0F3A38_P_2 */
+    { "vinserti128",   { XM, Vex256, EXxmm, Ib } },
+  },
+  {
+    /* VEX_W_0F3A39_P_2 */
+    { "vextracti128",  { EXxmm, XM, Ib } },
+  },
+  {

     /* VEX_W_0F3A40_P_2 */
     { "vdpps",         { XM, Vex, EXx, Ib } },
   },
     /* VEX_W_0F3A40_P_2 */
     { "vdpps",         { XM, Vex, EXx, Ib } },
   },


@@ -10281,13 +11487,17 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A42_P_2 */
   },
   {
     /* VEX_W_0F3A42_P_2 */

-    { "vmpsadbw",      { XM, Vex128, EXx, Ib } },
+    { "vmpsadbw",      { XM, Vex, EXx, Ib } },

   },
   {
     /* VEX_W_0F3A44_P_2 */
     { "vpclmulqdq",    { XM, Vex128, EXx, PCLMUL } },
   },
   {
   },
   {
     /* VEX_W_0F3A44_P_2 */
     { "vpclmulqdq",    { XM, Vex128, EXx, PCLMUL } },
   },
   {

+    /* VEX_W_0F3A46_P_2 */
+    { "vperm2i128",    { XM, Vex256, EXx, Ib } },
+  },
+  {

     /* VEX_W_0F3A48_P_2 */
     { "vpermil2ps",    { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
     { "vpermil2ps",    { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
     /* VEX_W_0F3A48_P_2 */
     { "vpermil2ps",    { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
     { "vpermil2ps",    { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },


@@ -10307,7 +11517,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A4C_P_2 */
   },
   {
     /* VEX_W_0F3A4C_P_2 */

-    { "vpblendvb",     { XM, Vex128, EXx, XMVexI4 } },
+    { "vpblendvb",     { XM, Vex, EXx, XMVexI4 } },

   },
   {
     /* VEX_W_0F3A60_P_2 */
   },
   {
     /* VEX_W_0F3A60_P_2 */


@@ -10329,6 +11539,9 @@ static const struct dis386 vex_w_table[][2] = {
     /* VEX_W_0F3ADF_P_2 */
     { "vaeskeygenassist", { XM, EXx, Ib } },
   },
     /* VEX_W_0F3ADF_P_2 */
     { "vaeskeygenassist", { XM, EXx, Ib } },
   },

+#define NEED_VEX_W_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_VEX_W_TABLE

 };
 
 static const struct dis386 mod_table[][2] = {
 };
 
 static const struct dis386 mod_table[][2] = {


@@ -10337,6 +11550,24 @@ static const struct dis386 mod_table[][2] = {
     { "leaS",          { Gv, M } },
   },
   {
     { "leaS",          { Gv, M } },
   },
   {

+    /* MOD_C6_REG_7 */
+    { Bad_Opcode },
+    { RM_TABLE (RM_C6_REG_7) },
+  },
+  {
+    /* MOD_C7_REG_7 */
+    { Bad_Opcode },
+    { RM_TABLE (RM_C7_REG_7) },
+  },
+  {
+    /* MOD_FF_REG_3 */
+    { "Jcall{T|}", { indirEp } },
+  },
+  {
+    /* MOD_FF_REG_5 */
+    { "Jjmp{T|}", { indirEp } },
+  },
+  {

     /* MOD_0F01_REG_0 */
     { X86_64_TABLE (X86_64_0F01_REG_0) },
     { RM_TABLE (RM_0F01_REG_0) },
     /* MOD_0F01_REG_0 */
     { X86_64_TABLE (X86_64_0F01_REG_0) },
     { RM_TABLE (RM_0F01_REG_0) },


@@ -10396,28 +11627,39 @@ static const struct dis386 mod_table[][2] = {
     { "prefetcht2",    { Mb } },
   },
   {
     { "prefetcht2",    { Mb } },
   },
   {

-    /* MOD_0F20 */
-    { Bad_Opcode },
-    { "movZ",          { Rm, Cm } },
+    /* MOD_0F18_REG_4 */
+    { "nop/reserved",  { Mb } },

   },
   {
   },
   {

-    /* MOD_0F21 */
-    { Bad_Opcode },
-    { "movZ",          { Rm, Dm } },
+    /* MOD_0F18_REG_5 */
+    { "nop/reserved",  { Mb } },

   },
   {
   },
   {

-    /* MOD_0F22 */
-    { Bad_Opcode },
-    { "movZ",          { Cm, Rm } },
+    /* MOD_0F18_REG_6 */
+    { "nop/reserved",  { Mb } },

   },
   {
   },
   {

-    /* MOD_0F23 */
-    { Bad_Opcode },
-    { "movZ",          { Dm, Rm } },
+    /* MOD_0F18_REG_7 */
+    { "nop/reserved",  { Mb } },
+  },
+  {
+    /* MOD_0F1A_PREFIX_0 */
+    { "bndldx",                { Gbnd, Ev_bnd } },
+    { "nopQ",          { Ev } },
+  },
+  {
+    /* MOD_0F1B_PREFIX_0 */
+    { "bndstx",                { Ev_bnd, Gbnd } },
+    { "nopQ",          { Ev } },
+  },
+  {
+    /* MOD_0F1B_PREFIX_1 */
+    { "bndmk",         { Gbnd, Ev_bnd } },
+    { "nopQ",          { Ev } },

   },
   {
     /* MOD_0F24 */
   },
   {
     /* MOD_0F24 */

-    { Bad_Opcode },    
+    { Bad_Opcode },

     { "movL",          { Rd, Td } },
   },
   {
     { "movL",          { Rd, Td } },
   },
   {


@@ -10527,12 +11769,12 @@ static const struct dis386 mod_table[][2] = {
   },
   {
     /* MOD_0FAE_REG_6 */
   },
   {
     /* MOD_0FAE_REG_6 */

-    { "xsaveopt",      { FXSAVE } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_6) },

     { RM_TABLE (RM_0FAE_REG_6) },
   },
   {
     /* MOD_0FAE_REG_7 */
     { RM_TABLE (RM_0FAE_REG_6) },
   },
   {
     /* MOD_0FAE_REG_7 */

-    { "clflush",       { Mb } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_7) },

     { RM_TABLE (RM_0FAE_REG_7) },
   },
   {
     { RM_TABLE (RM_0FAE_REG_7) },
   },
   {


@@ -10548,6 +11790,18 @@ static const struct dis386 mod_table[][2] = {
     { "lgsS",          { Gv, Mp } },
   },
   {
     { "lgsS",          { Gv, Mp } },
   },
   {

+    /* MOD_0FC7_REG_3 */
+    { "xrstors",               { FXSAVE } },
+  },
+  {
+    /* MOD_0FC7_REG_4 */
+    { "xsavec",                { FXSAVE } },
+  },
+  {
+    /* MOD_0FC7_REG_5 */
+    { "xsaves",                { FXSAVE } },
+  },
+  {

     /* MOD_0FC7_REG_6 */
     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
     { "rdrand",                { Ev } },
     /* MOD_0FC7_REG_6 */
     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
     { "rdrand",                { Ev } },


@@ -10555,6 +11809,7 @@ static const struct dis386 mod_table[][2] = {
   {
     /* MOD_0FC7_REG_7 */
     { "vmptrst",       { Mq } },
   {
     /* MOD_0FC7_REG_7 */
     { "vmptrst",       { Mq } },

+    { "rdseed",                { Ev } },

   },
   {
     /* MOD_0FD7 */
   },
   {
     /* MOD_0FD7 */


@@ -10576,6 +11831,7 @@ static const struct dis386 mod_table[][2] = {
   {
     /* MOD_62_32BIT */
     { "bound{S|}",     { Gv, Ma } },
   {
     /* MOD_62_32BIT */
     { "bound{S|}",     { Gv, Ma } },

+    { EVEX_TABLE (EVEX_0F) },

   },
   {
     /* MOD_C4_32BIT */
   },
   {
     /* MOD_C4_32BIT */


@@ -10675,7 +11931,7 @@ static const struct dis386 mod_table[][2] = {
   {
     /* MOD_VEX_0FD7_PREFIX_2 */
     { Bad_Opcode },
   {
     /* MOD_VEX_0FD7_PREFIX_2 */
     { Bad_Opcode },

-    { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) },
+    { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },

   },
   {
     /* MOD_VEX_0FE7_PREFIX_2 */
   },
   {
     /* MOD_VEX_0FE7_PREFIX_2 */


@@ -10686,20 +11942,12 @@ static const struct dis386 mod_table[][2] = {
     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
   },
   {
     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
   },
   {

-    /* MOD_VEX_0F3818_PREFIX_2 */
-    { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) },
-  },
-  {
-    /* MOD_VEX_0F3819_PREFIX_2 */
-    { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) },
-  },
-  {

     /* MOD_VEX_0F381A_PREFIX_2 */
     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
   },
   {
     /* MOD_VEX_0F382A_PREFIX_2 */
     /* MOD_VEX_0F381A_PREFIX_2 */
     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
   },
   {
     /* MOD_VEX_0F382A_PREFIX_2 */

-    { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) },
+    { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },

   },
   {
     /* MOD_VEX_0F382C_PREFIX_2 */
   },
   {
     /* MOD_VEX_0F382C_PREFIX_2 */


@@ -10717,10 +11965,33 @@ static const struct dis386 mod_table[][2] = {
     /* MOD_VEX_0F382F_PREFIX_2 */
     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
   },
     /* MOD_VEX_0F382F_PREFIX_2 */
     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
   },

+  {
+    /* MOD_VEX_0F385A_PREFIX_2 */
+    { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
+  },
+  {
+    /* MOD_VEX_0F388C_PREFIX_2 */
+    { "vpmaskmov%LW",  { XM, Vex, Mx } },
+  },
+  {
+    /* MOD_VEX_0F388E_PREFIX_2 */
+    { "vpmaskmov%LW",  { Mx, Vex, XM } },
+  },
+#define NEED_MOD_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_MOD_TABLE

 };
 
 static const struct dis386 rm_table[][8] = {
   {
 };
 
 static const struct dis386 rm_table[][8] = {
   {

+    /* RM_C6_REG_7 */
+    { "xabort",                { Skip_MODRM, Ib } },
+  },
+  {
+    /* RM_C7_REG_7 */
+    { "xbeginT",       { Skip_MODRM, Jv } },
+  },
+  {

     /* RM_0F01_REG_0 */
     { Bad_Opcode },
     { "vmcall",                { Skip_MODRM } },
     /* RM_0F01_REG_0 */
     { Bad_Opcode },
     { "vmcall",                { Skip_MODRM } },


@@ -10732,11 +12003,23 @@ static const struct dis386 rm_table[][8] = {
     /* RM_0F01_REG_1 */
     { "monitor",       { { OP_Monitor, 0 } } },
     { "mwait",         { { OP_Mwait, 0 } } },
     /* RM_0F01_REG_1 */
     { "monitor",       { { OP_Monitor, 0 } } },
     { "mwait",         { { OP_Mwait, 0 } } },

+    { "clac",          { Skip_MODRM } },
+    { "stac",          { Skip_MODRM } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "encls",         { Skip_MODRM } },

   },
   {
     /* RM_0F01_REG_2 */
     { "xgetbv",                { Skip_MODRM } },
     { "xsetbv",                { Skip_MODRM } },
   },
   {
     /* RM_0F01_REG_2 */
     { "xgetbv",                { Skip_MODRM } },
     { "xsetbv",                { Skip_MODRM } },

+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vmfunc",                { Skip_MODRM } },
+    { "xend",          { Skip_MODRM } },
+    { "xtest",         { Skip_MODRM } },
+    { "enclu",         { Skip_MODRM } },

   },
   {
     /* RM_0F01_REG_3 */
   },
   {
     /* RM_0F01_REG_3 */


@@ -10764,7 +12047,7 @@ static const struct dis386 rm_table[][8] = {
   },
   {
     /* RM_0FAE_REG_7 */
   },
   {
     /* RM_0FAE_REG_7 */

-    { "sfence",                { Skip_MODRM } },
+    { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },

   },
 };
 
   },
 };
 


@@ -10772,11 +12055,10 @@ static const struct dis386 rm_table[][8] = {
 
 /* We use the high bit to indicate different name for the same
    prefix.  */
 
 /* We use the high bit to indicate different name for the same
    prefix.  */

-#define ADDR16_PREFIX  (0x67 | 0x100)
-#define ADDR32_PREFIX  (0x67 | 0x200)
-#define DATA16_PREFIX  (0x66 | 0x100)
-#define DATA32_PREFIX  (0x66 | 0x200)

 #define REP_PREFIX     (0xf3 | 0x100)
 #define REP_PREFIX     (0xf3 | 0x100)

+#define XACQUIRE_PREFIX        (0xf2 | 0x200)
+#define XRELEASE_PREFIX        (0xf3 | 0x400)
+#define BND_PREFIX     (0xf2 | 0x400)

 
 static int
 ckprefix (void)
 
 static int
 ckprefix (void)


@@ -10794,6 +12076,8 @@ ckprefix (void)
   last_addr_prefix = -1;
   last_rex_prefix = -1;
   last_seg_prefix = -1;
   last_addr_prefix = -1;
   last_rex_prefix = -1;
   last_seg_prefix = -1;

+  fwait_prefix = -1;
+  active_seg_prefix = 0;

   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
     all_prefixes[i] = 0;
   i = 0;
   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
     all_prefixes[i] = 0;
   i = 0;


@@ -10843,26 +12127,32 @@ ckprefix (void)
        case 0x2e:
          prefixes |= PREFIX_CS;
          last_seg_prefix = i;
        case 0x2e:
          prefixes |= PREFIX_CS;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_CS;

          break;
        case 0x36:
          prefixes |= PREFIX_SS;
          last_seg_prefix = i;
          break;
        case 0x36:
          prefixes |= PREFIX_SS;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_SS;

          break;
        case 0x3e:
          prefixes |= PREFIX_DS;
          last_seg_prefix = i;
          break;
        case 0x3e:
          prefixes |= PREFIX_DS;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_DS;

          break;
        case 0x26:
          prefixes |= PREFIX_ES;
          last_seg_prefix = i;
          break;
        case 0x26:
          prefixes |= PREFIX_ES;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_ES;

          break;
        case 0x64:
          prefixes |= PREFIX_FS;
          last_seg_prefix = i;
          break;
        case 0x64:
          prefixes |= PREFIX_FS;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_FS;

          break;
        case 0x65:
          prefixes |= PREFIX_GS;
          last_seg_prefix = i;
          break;
        case 0x65:
          prefixes |= PREFIX_GS;
          last_seg_prefix = i;

+         active_seg_prefix = PREFIX_GS;

          break;
        case 0x66:
          prefixes |= PREFIX_DATA;
          break;
        case 0x66:
          prefixes |= PREFIX_DATA;


@@ -10876,10 +12166,14 @@ ckprefix (void)
          /* fwait is really an instruction.  If there are prefixes
             before the fwait, they belong to the fwait, *not* to the
             following instruction.  */
          /* fwait is really an instruction.  If there are prefixes
             before the fwait, they belong to the fwait, *not* to the
             following instruction.  */

+         fwait_prefix = i;

          if (prefixes || rex)
            {
              prefixes |= PREFIX_FWAIT;
              codep++;
          if (prefixes || rex)
            {
              prefixes |= PREFIX_FWAIT;
              codep++;

+             /* This ensures that the previous REX prefixes are noticed
+                as unused prefixes, as in the return case below.  */
+             rex_used = rex;

              return 1;
            }
          prefixes = PREFIX_FWAIT;
              return 1;
            }
          prefixes = PREFIX_FWAIT;


@@ -10902,28 +12196,6 @@ ckprefix (void)
   return 0;
 }
 
   return 0;
 }
 

-static int
-seg_prefix (int pref)
-{
-  switch (pref)
-    {
-    case 0x2e:
-      return PREFIX_CS;
-    case 0x36:
-      return PREFIX_SS;
-    case 0x3e:
-      return PREFIX_DS;
-    case 0x26:
-      return PREFIX_ES;
-    case 0x64:
-      return PREFIX_FS;
-    case 0x65:
-      return PREFIX_GS;
-    default:
-      return 0;
-    }
-}
-

 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
    prefix byte.  */
 
 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
    prefix byte.  */
 


@@ -10997,16 +12269,14 @@ prefix_name (int pref, int sizeflag)
        return (sizeflag & AFLAG) ? "addr16" : "addr32";
     case FWAIT_OPCODE:
       return "fwait";
        return (sizeflag & AFLAG) ? "addr16" : "addr32";
     case FWAIT_OPCODE:
       return "fwait";

-    case ADDR16_PREFIX:
-      return "addr16";
-    case ADDR32_PREFIX:
-      return "addr32";
-    case DATA16_PREFIX:
-      return "data16";
-    case DATA32_PREFIX:
-      return "data32";

     case REP_PREFIX:
       return "rep";
     case REP_PREFIX:
       return "rep";

+    case XACQUIRE_PREFIX:
+      return "xacquire";
+    case XRELEASE_PREFIX:
+      return "xrelease";
+    case BND_PREFIX:
+      return "bnd";

     default:
       return NULL;
     }
     default:
       return NULL;
     }


@@ -11137,34 +12407,49 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
              break;
            }
        }
              break;
            }
        }

-      else 
+      else

        {
        {

+         int last_prefix = -1;
+         int prefix = 0;

          vindex = 0;
          vindex = 0;

-         used_prefixes |= (prefixes & PREFIX_REPZ);
-         if (prefixes & PREFIX_REPZ)
-           {
-             vindex = 1;
-             all_prefixes[last_repz_prefix] = 0;
-           }
-         else
+         /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
+            When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
+            last one wins.  */
+         if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)

            {
            {

-             /* We should check PREFIX_REPNZ and PREFIX_REPZ before
-                PREFIX_DATA.  */
-             used_prefixes |= (prefixes & PREFIX_REPNZ);
-             if (prefixes & PREFIX_REPNZ)
+             if (last_repz_prefix > last_repnz_prefix)

                {
                {

-                 vindex = 3;
-                 all_prefixes[last_repnz_prefix] = 0;
+                 vindex = 1;
+                 prefix = PREFIX_REPZ;
+                 last_prefix = last_repz_prefix;

                }
              else
                {
                }
              else
                {

-                 used_prefixes |= (prefixes & PREFIX_DATA);
-                 if (prefixes & PREFIX_DATA)
-                   {
-                     vindex = 2;
-                     all_prefixes[last_data_prefix] = 0;
-                   }
+                 vindex = 3;
+                 prefix = PREFIX_REPNZ;
+                 last_prefix = last_repnz_prefix;

                }
                }

+
+             /* Ignore the invalid index if it isn't mandatory.  */
+             if (!mandatory_prefix
+                 && (prefix_table[dp->op[1].bytemode][vindex].name
+                     == NULL)
+                 && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
+                     == 0))
+               vindex = 0;
+           }
+
+         if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
+           {
+             vindex = 2;
+             prefix = PREFIX_DATA;
+             last_prefix = last_data_prefix;
+           }
+
+         if (vindex != 0)
+           {
+             used_prefixes |= prefix;
+             all_prefixes[last_prefix] = 0;

            }
        }
       dp = &prefix_table[dp->op[1].bytemode][vindex];
            }
        }
       dp = &prefix_table[dp->op[1].bytemode][vindex];


@@ -11179,6 +12464,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       FETCH_DATA (info, codep + 2);
       vindex = *codep++;
       dp = &three_byte_table[dp->op[1].bytemode][vindex];
       FETCH_DATA (info, codep + 2);
       vindex = *codep++;
       dp = &three_byte_table[dp->op[1].bytemode][vindex];

+      end_codep = codep;

       modrm.mod = (*codep >> 6) & 3;
       modrm.reg = (*codep >> 3) & 7;
       modrm.rm = *codep & 7;
       modrm.mod = (*codep >> 6) & 3;
       modrm.reg = (*codep >> 3) & 7;
       modrm.rm = *codep & 7;


@@ -11261,6 +12547,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       vindex = *codep++;
       dp = &xop_table[vex_table_index][vindex];
 
       vindex = *codep++;
       dp = &xop_table[vex_table_index][vindex];
 

+      end_codep = codep;

       FETCH_DATA (info, codep + 1);
       modrm.mod = (*codep >> 6) & 3;
       modrm.reg = (*codep >> 3) & 7;
       FETCH_DATA (info, codep + 1);
       modrm.mod = (*codep >> 6) & 3;
       modrm.reg = (*codep >> 3) & 7;


@@ -11268,6 +12555,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       break;
 
     case USE_VEX_C4_TABLE:
       break;
 
     case USE_VEX_C4_TABLE:

+      /* VEX prefix.  */

       FETCH_DATA (info, codep + 3);
       /* All bits in the REX prefix are ignored.  */
       rex_ignored = rex;
       FETCH_DATA (info, codep + 3);
       /* All bits in the REX prefix are ignored.  */
       rex_ignored = rex;


@@ -11321,6 +12609,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       codep++;
       vindex = *codep++;
       dp = &vex_table[vex_table_index][vindex];
       codep++;
       vindex = *codep++;
       dp = &vex_table[vex_table_index][vindex];

+      end_codep = codep;

       /* There is no MODRM byte for VEX [82|77].  */
       if (vindex != 0x77 && vindex != 0x82)
        {
       /* There is no MODRM byte for VEX [82|77].  */
       if (vindex != 0x77 && vindex != 0x82)
        {


@@ -11332,6 +12621,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       break;
 
     case USE_VEX_C5_TABLE:
       break;
 
     case USE_VEX_C5_TABLE:

+      /* VEX prefix.  */

       FETCH_DATA (info, codep + 2);
       /* All bits in the REX prefix are ignored.  */
       rex_ignored = rex;
       FETCH_DATA (info, codep + 2);
       /* All bits in the REX prefix are ignored.  */
       rex_ignored = rex;


@@ -11368,6 +12658,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       codep++;
       vindex = *codep++;
       dp = &vex_table[dp->op[1].bytemode][vindex];
       codep++;
       vindex = *codep++;
       dp = &vex_table[dp->op[1].bytemode][vindex];

+      end_codep = codep;

       /* There is no MODRM byte for VEX [82|77].  */
       if (vindex != 0x77 && vindex != 0x82)
        {
       /* There is no MODRM byte for VEX [82|77].  */
       if (vindex != 0x77 && vindex != 0x82)
        {


@@ -11385,6 +12676,111 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
       break;
 
       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
       break;
 

+    case USE_EVEX_TABLE:
+      two_source_ops = 0;
+      /* EVEX prefix.  */
+      vex.evex = 1;
+      FETCH_DATA (info, codep + 4);
+      /* All bits in the REX prefix are ignored.  */
+      rex_ignored = rex;
+      /* The first byte after 0x62.  */
+      rex = ~(*codep >> 5) & 0x7;
+      vex.r = *codep & 0x10;
+      switch ((*codep & 0xf))
+       {
+       default:
+         return &bad_opcode;
+       case 0x1:
+         vex_table_index = EVEX_0F;
+         break;
+       case 0x2:
+         vex_table_index = EVEX_0F38;
+         break;
+       case 0x3:
+         vex_table_index = EVEX_0F3A;
+         break;
+       }
+
+      /* The second byte after 0x62.  */
+      codep++;
+      vex.w = *codep & 0x80;
+      if (vex.w && address_mode == mode_64bit)
+       rex |= REX_W;
+
+      vex.register_specifier = (~(*codep >> 3)) & 0xf;
+      if (address_mode != mode_64bit)
+       {
+         /* In 16/32-bit mode silently ignore following bits.  */
+         rex &= ~REX_B;
+         vex.r = 1;
+         vex.v = 1;
+         vex.register_specifier &= 0x7;
+       }
+
+      /* The U bit.  */
+      if (!(*codep & 0x4))
+       return &bad_opcode;
+
+      switch ((*codep & 0x3))
+       {
+       case 0:
+         vex.prefix = 0;
+         break;
+       case 1:
+         vex.prefix = DATA_PREFIX_OPCODE;
+         break;
+       case 2:
+         vex.prefix = REPE_PREFIX_OPCODE;
+         break;
+       case 3:
+         vex.prefix = REPNE_PREFIX_OPCODE;
+         break;
+       }
+
+      /* The third byte after 0x62.  */
+      codep++;
+
+      /* Remember the static rounding bits.  */
+      vex.ll = (*codep >> 5) & 3;
+      vex.b = (*codep & 0x10) != 0;
+
+      vex.v = *codep & 0x8;
+      vex.mask_register_specifier = *codep & 0x7;
+      vex.zeroing = *codep & 0x80;
+
+      need_vex = 1;
+      need_vex_reg = 1;
+      codep++;
+      vindex = *codep++;
+      dp = &evex_table[vex_table_index][vindex];
+      end_codep = codep;
+      FETCH_DATA (info, codep + 1);
+      modrm.mod = (*codep >> 6) & 3;
+      modrm.reg = (*codep >> 3) & 7;
+      modrm.rm = *codep & 7;
+
+      /* Set vector length.  */
+      if (modrm.mod == 3 && vex.b)
+       vex.length = 512;
+      else
+       {
+         switch (vex.ll)
+           {
+           case 0x0:
+             vex.length = 128;
+             break;
+           case 0x1:
+             vex.length = 256;
+             break;
+           case 0x2:
+             vex.length = 512;
+             break;
+           default:
+             return &bad_opcode;
+           }
+       }
+      break;
+

     case 0:
       dp = &bad_opcode;
       break;
     case 0:
       dp = &bad_opcode;
       break;


@@ -11400,11 +12796,11 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 }
 
 static void
 }
 
 static void

-get_sib (disassemble_info *info)
+get_sib (disassemble_info *info, int sizeflag)

 {
   /* If modrm.mod == 3, operand must be register.  */
   if (need_modrm
 {
   /* If modrm.mod == 3, operand must be register.  */
   if (need_modrm

-      && address_mode != mode_16bit
+      && ((sizeflag & AFLAG) || address_mode == mode_64bit)

       && modrm.mod != 3
       && modrm.rm == 4)
     {
       && modrm.mod != 3
       && modrm.rm == 4)
     {


@@ -11422,41 +12818,24 @@ print_insn (bfd_vma pc, disassemble_info *info)
   int i;
   char *op_txt[MAX_OPERANDS];
   int needcomma;
   int i;
   char *op_txt[MAX_OPERANDS];
   int needcomma;

-  int sizeflag;
+  int sizeflag, orig_sizeflag;

   const char *p;
   struct dis_private priv;
   int prefix_length;
   const char *p;
   struct dis_private priv;
   int prefix_length;

-  int default_prefixes;
-
-  if (info->mach == bfd_mach_x86_64_intel_syntax
-      || info->mach == bfd_mach_x86_64
-      || info->mach == bfd_mach_x64_32_intel_syntax
-      || info->mach == bfd_mach_x64_32
-      || info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_l1om_intel_syntax)
-    address_mode = mode_64bit;
-  else
-    address_mode = mode_32bit;

 
 

-  if (intel_syntax == (char) -1)
-    intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
-                   || info->mach == bfd_mach_x86_64_intel_syntax
-                   || info->mach == bfd_mach_x64_32_intel_syntax
-                   || info->mach == bfd_mach_l1om_intel_syntax);
-
-  if (info->mach == bfd_mach_i386_i386
-      || info->mach == bfd_mach_x86_64
-      || info->mach == bfd_mach_x64_32
-      || info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_i386_i386_intel_syntax
-      || info->mach == bfd_mach_x86_64_intel_syntax
-      || info->mach == bfd_mach_x64_32_intel_syntax
-      || info->mach == bfd_mach_l1om_intel_syntax)
-    priv.orig_sizeflag = AFLAG | DFLAG;
+  priv.orig_sizeflag = AFLAG | DFLAG;
+  if ((info->mach & bfd_mach_i386_i386) != 0)
+    address_mode = mode_32bit;

   else if (info->mach == bfd_mach_i386_i8086)
   else if (info->mach == bfd_mach_i386_i8086)

-    priv.orig_sizeflag = 0;
+    {
+      address_mode = mode_16bit;
+      priv.orig_sizeflag = 0;
+    }

   else
   else

-    abort ();
+    address_mode = mode_64bit;
+
+  if (intel_syntax == (char) -1)
+    intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;

 
   for (p = info->disassembler_options; p != NULL; )
     {
 
   for (p = info->disassembler_options; p != NULL; )
     {


@@ -11528,10 +12907,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
       names8rex = intel_names8rex;
       names_seg = intel_names_seg;
       names_mm = intel_names_mm;
       names8rex = intel_names8rex;
       names_seg = intel_names_seg;
       names_mm = intel_names_mm;

+      names_bnd = intel_names_bnd;

       names_xmm = intel_names_xmm;
       names_ymm = intel_names_ymm;
       names_xmm = intel_names_xmm;
       names_ymm = intel_names_ymm;

+      names_zmm = intel_names_zmm;

       index64 = intel_index64;
       index32 = intel_index32;
       index64 = intel_index64;
       index32 = intel_index32;

+      names_mask = intel_names_mask;

       index16 = intel_index16;
       open_char = '[';
       close_char = ']';
       index16 = intel_index16;
       open_char = '[';
       close_char = ']';


@@ -11547,10 +12929,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
       names8rex = att_names8rex;
       names_seg = att_names_seg;
       names_mm = att_names_mm;
       names8rex = att_names8rex;
       names_seg = att_names_seg;
       names_mm = att_names_mm;

+      names_bnd = att_names_bnd;

       names_xmm = att_names_xmm;
       names_ymm = att_names_ymm;
       names_xmm = att_names_xmm;
       names_ymm = att_names_ymm;

+      names_zmm = att_names_zmm;

       index64 = att_index64;
       index32 = att_index32;
       index64 = att_index64;
       index32 = att_index32;

+      names_mask = att_names_mask;

       index16 = att_index16;
       open_char = '(';
       close_char =  ')';
       index16 = att_index16;
       open_char = '(';
       close_char =  ')';


@@ -11561,8 +12946,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
   /* The output looks better if we put 7 bytes on a line, since that
      puts most long word instructions on a single line.  Use 8 bytes
      for Intel L1OM.  */
   /* The output looks better if we put 7 bytes on a line, since that
      puts most long word instructions on a single line.  Use 8 bytes
      for Intel L1OM.  */

-  if (info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_l1om_intel_syntax)
+  if ((info->mach & bfd_mach_l1om) != 0)

     info->bytes_per_line = 8;
   else
     info->bytes_per_line = 7;
     info->bytes_per_line = 8;
   else
     info->bytes_per_line = 7;


@@ -11583,7 +12967,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
   start_codep = priv.the_buffer;
   codep = priv.the_buffer;
 
   start_codep = priv.the_buffer;
   codep = priv.the_buffer;
 

-  if (setjmp (priv.bailout) != 0)
+  if (OPCODES_SIGSETJMP (priv.bailout) != 0)

     {
       const char *name;
 
     {
       const char *name;
 


@@ -11615,11 +12999,12 @@ print_insn (bfd_vma pc, disassemble_info *info)
     {
       /* Too many prefixes or unused REX prefixes.  */
       for (i = 0;
     {
       /* Too many prefixes or unused REX prefixes.  */
       for (i = 0;

-          all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
+          i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];

           i++)
           i++)

-       (*info->fprintf_func) (info->stream, "%s",
+       (*info->fprintf_func) (info->stream, "%s%s",
+                              i == 0 ? "" : " ",

                               prefix_name (all_prefixes[i], sizeflag));
                               prefix_name (all_prefixes[i], sizeflag));

-      return 1;
+      return i;

     }
 
   insn_codep = codep;
     }
 
   insn_codep = codep;


@@ -11630,8 +13015,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
   if (((prefixes & PREFIX_FWAIT)
        && ((*codep < 0xd8) || (*codep > 0xdf))))
     {
   if (((prefixes & PREFIX_FWAIT)
        && ((*codep < 0xd8) || (*codep > 0xdf))))
     {

+      /* Handle prefixes before fwait.  */
+      for (i = 0; i < fwait_prefix && all_prefixes[i];
+          i++)
+       (*info->fprintf_func) (info->stream, "%s ",
+                              prefix_name (all_prefixes[i], sizeflag));

       (*info->fprintf_func) (info->stream, "fwait");
       (*info->fprintf_func) (info->stream, "fwait");

-      return 1;
+      return i + 1;

     }
 
   if (*codep == 0x0f)
     }
 
   if (*codep == 0x0f)


@@ -11641,56 +13031,27 @@ print_insn (bfd_vma pc, disassemble_info *info)
       threebyte = *++codep;
       dp = &dis386_twobyte[threebyte];
       need_modrm = twobyte_has_modrm[*codep];
       threebyte = *++codep;
       dp = &dis386_twobyte[threebyte];
       need_modrm = twobyte_has_modrm[*codep];

+      mandatory_prefix = twobyte_has_mandatory_prefix[*codep];

       codep++;
     }
   else
     {
       dp = &dis386[*codep];
       need_modrm = onebyte_has_modrm[*codep];
       codep++;
     }
   else
     {
       dp = &dis386[*codep];
       need_modrm = onebyte_has_modrm[*codep];

+      mandatory_prefix = 0;

       codep++;
     }
 
       codep++;
     }
 

-  if ((prefixes & PREFIX_REPZ))
-    used_prefixes |= PREFIX_REPZ;
-  if ((prefixes & PREFIX_REPNZ))
-    used_prefixes |= PREFIX_REPNZ;
-  if ((prefixes & PREFIX_LOCK))
-    used_prefixes |= PREFIX_LOCK;
-
-  default_prefixes = 0;
+  /* Save sizeflag for printing the extra prefixes later before updating
+     it for mnemonic and operand processing.  The prefix names depend
+     only on the address mode.  */
+  orig_sizeflag = sizeflag;

   if (prefixes & PREFIX_ADDR)
   if (prefixes & PREFIX_ADDR)

-    {
-      sizeflag ^= AFLAG;
-      if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
-       {
-         if ((sizeflag & AFLAG) || address_mode == mode_64bit)
-           all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
-         else
-           all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
-         default_prefixes |= PREFIX_ADDR;
-       }
-    }
-
+    sizeflag ^= AFLAG;

   if ((prefixes & PREFIX_DATA))
   if ((prefixes & PREFIX_DATA))

-    {
-      sizeflag ^= DFLAG;
-      if (dp->op[2].bytemode == cond_jump_mode
-         && dp->op[0].bytemode == v_mode
-         && !intel_syntax)
-       {
-         if (sizeflag & DFLAG)
-           all_prefixes[last_data_prefix] = DATA32_PREFIX;
-         else
-           all_prefixes[last_data_prefix] = DATA16_PREFIX;
-         default_prefixes |= PREFIX_DATA;
-       }
-      else if (rex & REX_W)
-       {
-         /* REX_W will override PREFIX_DATA.  */
-         default_prefixes |= PREFIX_DATA;
-       }
-    }
+    sizeflag ^= DFLAG;

 
 

+  end_codep = codep;

   if (need_modrm)
     {
       FETCH_DATA (info, codep + 1);
   if (need_modrm)
     {
       FETCH_DATA (info, codep + 1);


@@ -11699,58 +13060,54 @@ print_insn (bfd_vma pc, disassemble_info *info)
       modrm.rm = *codep & 7;
     }
 
       modrm.rm = *codep & 7;
     }
 

-   need_vex = 0;
-   need_vex_reg = 0;
-   vex_w_done = 0;
+  need_vex = 0;
+  need_vex_reg = 0;
+  vex_w_done = 0;
+  vex.evex = 0;

 
   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
     {
 
   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
     {

-      get_sib (info);
+      get_sib (info, sizeflag);

       dofloat (sizeflag);
     }
   else
     {
       dp = get_valid_dis386 (dp, info);
       if (dp != NULL && putop (dp->name, sizeflag) == 0)
       dofloat (sizeflag);
     }
   else
     {
       dp = get_valid_dis386 (dp, info);
       if (dp != NULL && putop (dp->name, sizeflag) == 0)

-        {
-         get_sib (info);
+       {
+         get_sib (info, sizeflag);

          for (i = 0; i < MAX_OPERANDS; ++i)
            {
              obufp = op_out[i];
              op_ad = MAX_OPERANDS - 1 - i;
              if (dp->op[i].rtn)
                (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
          for (i = 0; i < MAX_OPERANDS; ++i)
            {
              obufp = op_out[i];
              op_ad = MAX_OPERANDS - 1 - i;
              if (dp->op[i].rtn)
                (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);

+             /* For EVEX instruction after the last operand masking
+                should be printed.  */
+             if (i == 0 && vex.evex)
+               {
+                 /* Don't print {%k0}.  */
+                 if (vex.mask_register_specifier)
+                   {
+                     oappend ("{");
+                     oappend (names_mask[vex.mask_register_specifier]);
+                     oappend ("}");
+                   }
+                 if (vex.zeroing)
+                   oappend ("{z}");
+               }

            }
        }
     }
 
            }
        }
     }
 

-  /* See if any prefixes were not used.  If so, print the first one
-     separately.  If we don't do this, we'll wind up printing an
-     instruction stream which does not precisely correspond to the
-     bytes we are disassembling.  */
-  if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
-    {
-      for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
-       if (all_prefixes[i])
-         {
-           const char *name;
-           name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
-           if (name == NULL)
-             name = INTERNAL_DISASSEMBLER_ERROR;
-           (*info->fprintf_func) (info->stream, "%s", name);
-           return 1;
-         }
-    }
-

   /* Check if the REX prefix is used.  */
   /* Check if the REX prefix is used.  */

-  if (rex_ignored == 0 && (rex ^ rex_used) == 0)
+  if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)

     all_prefixes[last_rex_prefix] = 0;
 
   /* Check if the SEG prefix is used.  */
   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
                   | PREFIX_FS | PREFIX_GS)) != 0
     all_prefixes[last_rex_prefix] = 0;
 
   /* Check if the SEG prefix is used.  */
   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
                   | PREFIX_FS | PREFIX_GS)) != 0

-      && (used_prefixes
-         & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
+      && (used_prefixes & active_seg_prefix) != 0)

     all_prefixes[last_seg_prefix] = 0;
 
   /* Check if the ADDR prefix is used.  */
     all_prefixes[last_seg_prefix] = 0;
 
   /* Check if the ADDR prefix is used.  */


@@ -11763,18 +13120,39 @@ print_insn (bfd_vma pc, disassemble_info *info)
       && (used_prefixes & PREFIX_DATA) != 0)
     all_prefixes[last_data_prefix] = 0;
 
       && (used_prefixes & PREFIX_DATA) != 0)
     all_prefixes[last_data_prefix] = 0;
 

+  /* Print the extra prefixes.  */

   prefix_length = 0;
   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
     if (all_prefixes[i])
       {
        const char *name;
   prefix_length = 0;
   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
     if (all_prefixes[i])
       {
        const char *name;

-       name = prefix_name (all_prefixes[i], sizeflag);
+       name = prefix_name (all_prefixes[i], orig_sizeflag);

        if (name == NULL)
          abort ();
        prefix_length += strlen (name) + 1;
        (*info->fprintf_func) (info->stream, "%s ", name);
       }
 
        if (name == NULL)
          abort ();
        prefix_length += strlen (name) + 1;
        (*info->fprintf_func) (info->stream, "%s ", name);
       }
 

+  /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
+     unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
+     used by putop and MMX/SSE operand and may be overriden by the
+     PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
+     separately.  */
+  if (mandatory_prefix
+      && dp != &bad_opcode
+      && (((prefixes
+           & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
+          && (used_prefixes
+              & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
+         || ((((prefixes
+                & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+               == PREFIX_DATA)
+              && (used_prefixes & PREFIX_DATA) == 0))))
+    {
+      (*info->fprintf_func) (info->stream, "(bad)");
+      return end_codep - priv.the_buffer;
+    }
+

   /* Check maximum code length.  */
   if ((codep - start_codep) > MAX_CODE_LENGTH)
     {
   /* Check maximum code length.  */
   if ((codep - start_codep) > MAX_CODE_LENGTH)
     {


@@ -11795,13 +13173,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
       bfd_vma riprel;
 
       for (i = 0; i < MAX_OPERANDS; ++i)
       bfd_vma riprel;
 
       for (i = 0; i < MAX_OPERANDS; ++i)

-        op_txt[i] = op_out[i];
+       op_txt[i] = op_out[i];

 
       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
        {
 
       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
        {

-          op_ad = op_index[i];
-          op_index[i] = op_index[MAX_OPERANDS - 1 - i];
-          op_index[MAX_OPERANDS - 1 - i] = op_ad;
+         op_ad = op_index[i];
+         op_index[i] = op_index[MAX_OPERANDS - 1 - i];
+         op_index[MAX_OPERANDS - 1 - i] = op_ad;

          riprel = op_riprel[i];
          op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
          op_riprel[MAX_OPERANDS - 1 - i] = riprel;
          riprel = op_riprel[i];
          op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
          op_riprel[MAX_OPERANDS - 1 - i] = riprel;


@@ -11810,7 +13188,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
   else
     {
       for (i = 0; i < MAX_OPERANDS; ++i)
   else
     {
       for (i = 0; i < MAX_OPERANDS; ++i)

-        op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
+       op_txt[MAX_OPERANDS - 1 - i] = op_out[i];

     }
 
   needcomma = 0;
     }
 
   needcomma = 0;


@@ -12203,17 +13581,25 @@ dofloat (int sizeflag)
     }
 }
 
     }
 }
 

+/* Like oappend (below), but S is a string starting with '%'.
+   In Intel syntax, the '%' is elided.  */
+static void
+oappend_maybe_intel (const char *s)
+{
+  oappend (s + intel_syntax);
+}
+

 static void
 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {
 static void
 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {

-  oappend ("%st" + intel_syntax);
+  oappend_maybe_intel ("%st");

 }
 
 static void
 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {
   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
 }
 
 static void
 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {
   sprintf (scratchbuf, "%%st(%d)", modrm.rm);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

 }
 
 /* Capital letters in template are macros.  */
 }
 
 /* Capital letters in template are macros.  */


@@ -12442,45 +13828,76 @@ case_L:
        case 'T':
          if (!intel_syntax
              && address_mode == mode_64bit
        case 'T':
          if (!intel_syntax
              && address_mode == mode_64bit

-             && (sizeflag & DFLAG))
+             && ((sizeflag & DFLAG) || (rex & REX_W)))

            {
              *obufp++ = 'q';
              break;
            }
          /* Fall through.  */
            {
              *obufp++ = 'q';
              break;
            }
          /* Fall through.  */

+         goto case_P;

        case 'P':
        case 'P':

-         if (intel_syntax)
+         if (l == 0 && len == 1)

            {
            {

-             if ((rex & REX_W) == 0
-                 && (prefixes & PREFIX_DATA))
+case_P:
+             if (intel_syntax)

                {
                {

-                 if ((sizeflag & DFLAG) == 0)
-                   *obufp++ = 'w';
-                  used_prefixes |= (prefixes & PREFIX_DATA);
+                 if ((rex & REX_W) == 0
+                     && (prefixes & PREFIX_DATA))
+                   {
+                     if ((sizeflag & DFLAG) == 0)
+                       *obufp++ = 'w';
+                     used_prefixes |= (prefixes & PREFIX_DATA);
+                   }
+                 break;
+               }
+             if ((prefixes & PREFIX_DATA)
+                 || (rex & REX_W)
+                 || (sizeflag & SUFFIX_ALWAYS))
+               {
+                 USED_REX (REX_W);
+                 if (rex & REX_W)
+                   *obufp++ = 'q';
+                 else
+                   {
+                     if (sizeflag & DFLAG)
+                       *obufp++ = 'l';
+                     else
+                       *obufp++ = 'w';
+                     used_prefixes |= (prefixes & PREFIX_DATA);
+                   }

                }
                }

-             break;

            }
            }

-         if ((prefixes & PREFIX_DATA)
-             || (rex & REX_W)
-             || (sizeflag & SUFFIX_ALWAYS))
+         else

            {
            {

-             USED_REX (REX_W);
-             if (rex & REX_W)
-               *obufp++ = 'q';
-             else
+             if (l != 1 || len != 2 || last[0] != 'L')
+               {
+                 SAVE_LAST (*p);
+                 break;
+               }
+
+             if ((prefixes & PREFIX_DATA)
+                 || (rex & REX_W)
+                 || (sizeflag & SUFFIX_ALWAYS))

                {
                {

-                  if (sizeflag & DFLAG)
-                     *obufp++ = 'l';
-                  else
-                    *obufp++ = 'w';
-                  used_prefixes |= (prefixes & PREFIX_DATA);
+                 USED_REX (REX_W);
+                 if (rex & REX_W)
+                   *obufp++ = 'q';
+                 else
+                   {
+                     if (sizeflag & DFLAG)
+                       *obufp++ = intel_syntax ? 'd' : 'l';
+                     else
+                       *obufp++ = 'w';
+                     used_prefixes |= (prefixes & PREFIX_DATA);
+                   }

                }
            }
          break;
        case 'U':
          if (intel_syntax)
            break;
                }
            }
          break;
        case 'U':
          if (intel_syntax)
            break;

-         if (address_mode == mode_64bit && (sizeflag & DFLAG))
+         if (address_mode == mode_64bit
+             && ((sizeflag & DFLAG) || (rex & REX_W)))

            {
              if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
                *obufp++ = 'q';
            {
              if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
                *obufp++ = 'q';


@@ -12552,7 +13969,8 @@ case_Q:
            {
              if (intel_syntax)
                break;
            {
              if (intel_syntax)
                break;

-             if (address_mode == mode_64bit && (sizeflag & DFLAG))
+             if (address_mode == mode_64bit
+                 && ((sizeflag & DFLAG) || (rex & REX_W)))

                {
                  if (sizeflag & SUFFIX_ALWAYS)
                    *obufp++ = 'q';
                {
                  if (sizeflag & SUFFIX_ALWAYS)
                    *obufp++ = 'q';


@@ -12699,14 +14117,20 @@ case_S:
            }
          else
            {
            }
          else
            {

-             if (l != 1 || len != 2 || last[0] != 'X')
+             if (l != 1
+                 || len != 2
+                 || (last[0] != 'X'
+                     && last[0] != 'L'))

                {
                  SAVE_LAST (*p);
                  break;
                }
              if (!need_vex)
                abort ();
                {
                  SAVE_LAST (*p);
                  break;
                }
              if (!need_vex)
                abort ();

-             *obufp++ = vex.w ? 'd': 's';
+             if (last[0] == 'X')
+               *obufp++ = vex.w ? 'd': 's';
+             else
+               *obufp++ = vex.w ? 'q': 'd';

            }
          break;
        }
            }
          break;
        }


@@ -12726,35 +14150,33 @@ oappend (const char *s)
 static void
 append_seg (void)
 {
 static void
 append_seg (void)
 {

-  if (prefixes & PREFIX_CS)
-    {
-      used_prefixes |= PREFIX_CS;
-      oappend ("%cs:" + intel_syntax);
-    }
-  if (prefixes & PREFIX_DS)
-    {
-      used_prefixes |= PREFIX_DS;
-      oappend ("%ds:" + intel_syntax);
-    }
-  if (prefixes & PREFIX_SS)
-    {
-      used_prefixes |= PREFIX_SS;
-      oappend ("%ss:" + intel_syntax);
-    }
-  if (prefixes & PREFIX_ES)
-    {
-      used_prefixes |= PREFIX_ES;
-      oappend ("%es:" + intel_syntax);
-    }
-  if (prefixes & PREFIX_FS)
-    {
-      used_prefixes |= PREFIX_FS;
-      oappend ("%fs:" + intel_syntax);
-    }
-  if (prefixes & PREFIX_GS)
+  /* Only print the active segment register.  */
+  if (!active_seg_prefix)
+    return;
+
+  used_prefixes |= active_seg_prefix;
+  switch (active_seg_prefix)

     {
     {

-      used_prefixes |= PREFIX_GS;
-      oappend ("%gs:" + intel_syntax);
+    case PREFIX_CS:
+      oappend_maybe_intel ("%cs:");
+      break;
+    case PREFIX_DS:
+      oappend_maybe_intel ("%ds:");
+      break;
+    case PREFIX_SS:
+      oappend_maybe_intel ("%ss:");
+      break;
+    case PREFIX_ES:
+      oappend_maybe_intel ("%es:");
+      break;
+    case PREFIX_FS:
+      oappend_maybe_intel ("%fs:");
+      break;
+    case PREFIX_GS:
+      oappend_maybe_intel ("%gs:");
+      break;
+    default:
+      break;

     }
 }
 
     }
 }
 


@@ -12870,19 +14292,33 @@ print_displacement (char *buf, bfd_vma disp)
 static void
 intel_operand_size (int bytemode, int sizeflag)
 {
 static void
 intel_operand_size (int bytemode, int sizeflag)
 {

+  if (vex.evex
+      && vex.b
+      && (bytemode == x_mode
+         || bytemode == evex_half_bcst_xmmq_mode))
+    {
+      if (vex.w)
+       oappend ("QWORD PTR ");
+      else
+       oappend ("DWORD PTR ");
+      return;
+    }

   switch (bytemode)
     {
     case b_mode:
     case b_swap_mode:
     case dqb_mode:
   switch (bytemode)
     {
     case b_mode:
     case b_swap_mode:
     case dqb_mode:

+    case db_mode:

       oappend ("BYTE PTR ");
       break;
     case w_mode:
       oappend ("BYTE PTR ");
       break;
     case w_mode:

+    case dw_mode:

     case dqw_mode:
     case dqw_mode:

+    case dqw_swap_mode:

       oappend ("WORD PTR ");
       break;
     case stack_v_mode:
       oappend ("WORD PTR ");
       break;
     case stack_v_mode:

-      if (address_mode == mode_64bit && (sizeflag & DFLAG))
+      if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))

        {
          oappend ("QWORD PTR ");
          break;
        {
          oappend ("QWORD PTR ");
          break;


@@ -12948,6 +14384,8 @@ intel_operand_size (int bytemode, int sizeflag)
       break;
     case x_mode:
     case x_swap_mode:
       break;
     case x_mode:
     case x_swap_mode:

+    case evex_x_gscat_mode:
+    case evex_x_nobcst_mode:

       if (need_vex)
        {
          switch (vex.length)
       if (need_vex)
        {
          switch (vex.length)


@@ -12958,6 +14396,9 @@ intel_operand_size (int bytemode, int sizeflag)
            case 256:
              oappend ("YMMWORD PTR ");
              break;
            case 256:
              oappend ("YMMWORD PTR ");
              break;

+           case 512:
+             oappend ("ZMMWORD PTR ");
+             break;

            default:
              abort ();
            }
            default:
              abort ();
            }


@@ -12968,16 +14409,121 @@ intel_operand_size (int bytemode, int sizeflag)
     case xmm_mode:
       oappend ("XMMWORD PTR ");
       break;
     case xmm_mode:
       oappend ("XMMWORD PTR ");
       break;

+    case ymm_mode:
+      oappend ("YMMWORD PTR ");
+      break;

     case xmmq_mode:
     case xmmq_mode:

+    case evex_half_bcst_xmmq_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+         oappend ("QWORD PTR ");
+         break;
+       case 256:
+         oappend ("XMMWORD PTR ");
+         break;
+       case 512:
+         oappend ("YMMWORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case xmm_mb_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+       case 512:
+         oappend ("BYTE PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case xmm_mw_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+       case 512:
+         oappend ("WORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case xmm_md_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+       case 512:
+         oappend ("DWORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case xmm_mq_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+       case 512:
+         oappend ("QWORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case xmmdw_mode:

       if (!need_vex)
        abort ();
 
       switch (vex.length)
        {
        case 128:
       if (!need_vex)
        abort ();
 
       switch (vex.length)
        {
        case 128:

+         oappend ("WORD PTR ");
+         break;
+       case 256:
+         oappend ("DWORD PTR ");
+         break;
+       case 512:

          oappend ("QWORD PTR ");
          break;
          oappend ("QWORD PTR ");
          break;

+       default:
+         abort ();
+       }
+      break;
+    case xmmqd_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+         oappend ("DWORD PTR ");
+         break;

        case 256:
        case 256:

+         oappend ("QWORD PTR ");
+         break;
+       case 512:

          oappend ("XMMWORD PTR ");
          break;
        default:
          oappend ("XMMWORD PTR ");
          break;
        default:


@@ -12996,6 +14542,23 @@ intel_operand_size (int bytemode, int sizeflag)
        case 256:
          oappend ("YMMWORD PTR ");
          break;
        case 256:
          oappend ("YMMWORD PTR ");
          break;

+       case 512:
+         oappend ("ZMMWORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+      break;
+    case ymmxmm_mode:
+      if (!need_vex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+         oappend ("XMMWORD PTR ");
+         break;

        default:
          abort ();
        }
        default:
          abort ();
        }


@@ -13003,6 +14566,7 @@ intel_operand_size (int bytemode, int sizeflag)
     case o_mode:
       oappend ("OWORD PTR ");
       break;
     case o_mode:
       oappend ("OWORD PTR ");
       break;

+    case xmm_mdq_mode:

     case vex_w_dq_mode:
     case vex_scalar_w_dq_mode:
       if (!need_vex)
     case vex_w_dq_mode:
     case vex_scalar_w_dq_mode:
       if (!need_vex)


@@ -13013,6 +14577,74 @@ intel_operand_size (int bytemode, int sizeflag)
       else
        oappend ("DWORD PTR ");
       break;
       else
        oappend ("DWORD PTR ");
       break;

+    case vex_vsib_d_w_dq_mode:
+    case vex_vsib_q_w_dq_mode:
+      if (!need_vex)
+       abort ();
+
+      if (!vex.evex)
+       {
+         if (vex.w)
+           oappend ("QWORD PTR ");
+         else
+           oappend ("DWORD PTR ");
+       }
+      else
+       {
+         switch (vex.length)
+           {
+           case 128:
+             oappend ("XMMWORD PTR ");
+             break;
+           case 256:
+             oappend ("YMMWORD PTR ");
+             break;
+           case 512:
+             oappend ("ZMMWORD PTR ");
+             break;
+           default:
+             abort ();
+           }
+       }
+      break;
+    case vex_vsib_q_w_d_mode:
+    case vex_vsib_d_w_d_mode:
+      if (!need_vex || !vex.evex)
+       abort ();
+
+      switch (vex.length)
+       {
+       case 128:
+         oappend ("QWORD PTR ");
+         break;
+       case 256:
+         oappend ("XMMWORD PTR ");
+         break;
+       case 512:
+         oappend ("YMMWORD PTR ");
+         break;
+       default:
+         abort ();
+       }
+
+      break;
+    case mask_bd_mode:
+      if (!need_vex || vex.length != 128)
+       abort ();
+      if (vex.w)
+       oappend ("DWORD PTR ");
+      else
+       oappend ("BYTE PTR ");
+      break;
+    case mask_mode:
+      if (!need_vex)
+       abort ();
+      if (vex.w)
+       oappend ("QWORD PTR ");
+      else
+       oappend ("WORD PTR ");
+      break;
+    case v_bnd_mode:

     default:
       break;
     }
     default:
       break;
     }


@@ -13029,7 +14661,9 @@ OP_E_register (int bytemode, int sizeflag)
     reg += 8;
 
   if ((sizeflag & SUFFIX_ALWAYS)
     reg += 8;
 
   if ((sizeflag & SUFFIX_ALWAYS)

-      && (bytemode == b_swap_mode || bytemode == v_swap_mode))
+      && (bytemode == b_swap_mode
+         || bytemode == v_swap_mode
+         || bytemode == dqw_swap_mode))

     swap_operand ();
 
   switch (bytemode)
     swap_operand ();
 
   switch (bytemode)


@@ -13046,16 +14680,22 @@ OP_E_register (int bytemode, int sizeflag)
       names = names16;
       break;
     case d_mode:
       names = names16;
       break;
     case d_mode:

+    case dw_mode:
+    case db_mode:

       names = names32;
       break;
     case q_mode:
       names = names64;
       break;
     case m_mode:
       names = names32;
       break;
     case q_mode:
       names = names64;
       break;
     case m_mode:

+    case v_bnd_mode:

       names = address_mode == mode_64bit ? names64 : names32;
       break;
       names = address_mode == mode_64bit ? names64 : names32;
       break;

+    case bnd_mode:
+      names = names_bnd;
+      break;

     case stack_v_mode:
     case stack_v_mode:

-      if (address_mode == mode_64bit && (sizeflag & DFLAG))
+      if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))

        {
          names = names64;
          break;
        {
          names = names64;
          break;


@@ -13068,12 +14708,13 @@ OP_E_register (int bytemode, int sizeflag)
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:

+    case dqw_swap_mode:

       USED_REX (REX_W);
       if (rex & REX_W)
        names = names64;
       else
        {
       USED_REX (REX_W);
       if (rex & REX_W)
        names = names64;
       else
        {

-         if ((sizeflag & DFLAG) 
+         if ((sizeflag & DFLAG)

              || (bytemode != v_mode
                  && bytemode != v_swap_mode))
            names = names32;
              || (bytemode != v_mode
                  && bytemode != v_swap_mode))
            names = names32;


@@ -13081,22 +14722,136 @@ OP_E_register (int bytemode, int sizeflag)
            names = names16;
          used_prefixes |= (prefixes & PREFIX_DATA);
        }
            names = names16;
          used_prefixes |= (prefixes & PREFIX_DATA);
        }

-      break;
-    case 0:
-      return;
-    default:
-      oappend (INTERNAL_DISASSEMBLER_ERROR);
-      return;
+      break;
+    case mask_bd_mode:
+    case mask_mode:
+      names = names_mask;
+      break;
+    case 0:
+      return;
+    default:
+      oappend (INTERNAL_DISASSEMBLER_ERROR);
+      return;
+    }
+  oappend (names[reg]);
+}
+
+static void
+OP_E_memory (int bytemode, int sizeflag)
+{
+  bfd_vma disp = 0;
+  int add = (rex & REX_B) ? 8 : 0;
+  int riprel = 0;
+  int shift;
+
+  if (vex.evex)
+    {
+      /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
+      if (vex.b
+         && bytemode != x_mode
+         && bytemode != xmmq_mode
+         && bytemode != evex_half_bcst_xmmq_mode)
+       {
+         BadOp ();
+         return;
+       }
+      switch (bytemode)
+       {
+       case dqw_mode:
+       case dw_mode:
+       case dqw_swap_mode:
+         shift = 1;
+         break;
+       case dqb_mode:
+       case db_mode:
+         shift = 0;
+         break;
+       case vex_vsib_d_w_dq_mode:
+       case vex_vsib_d_w_d_mode:
+       case vex_vsib_q_w_dq_mode:
+       case vex_vsib_q_w_d_mode:
+       case evex_x_gscat_mode:
+       case xmm_mdq_mode:
+         shift = vex.w ? 3 : 2;
+         break;
+       case x_mode:
+       case evex_half_bcst_xmmq_mode:
+       case xmmq_mode:
+         if (vex.b)
+           {
+             shift = vex.w ? 3 : 2;
+             break;
+           }
+         /* Fall through if vex.b == 0.  */
+       case xmmqd_mode:
+       case xmmdw_mode:
+       case ymmq_mode:
+       case evex_x_nobcst_mode:
+       case x_swap_mode:
+         switch (vex.length)
+           {
+           case 128:
+             shift = 4;
+             break;
+           case 256:
+             shift = 5;
+             break;
+           case 512:
+             shift = 6;
+             break;
+           default:
+             abort ();
+           }
+         break;
+       case ymm_mode:
+         shift = 5;
+         break;
+       case xmm_mode:
+         shift = 4;
+         break;
+       case xmm_mq_mode:
+       case q_mode:
+       case q_scalar_mode:
+       case q_swap_mode:
+       case q_scalar_swap_mode:
+         shift = 3;
+         break;
+       case dqd_mode:
+       case xmm_md_mode:
+       case d_mode:
+       case d_scalar_mode:
+       case d_swap_mode:
+       case d_scalar_swap_mode:
+         shift = 2;
+         break;
+       case xmm_mw_mode:
+         shift = 1;
+         break;
+       case xmm_mb_mode:
+         shift = 0;
+         break;
+       default:
+         abort ();
+       }
+      /* Make necessary corrections to shift for modes that need it.
+        For these modes we currently have shift 4, 5 or 6 depending on
+        vex.length (it corresponds to xmmword, ymmword or zmmword
+        operand).  We might want to make it 3, 4 or 5 (e.g. for
+        xmmq_mode).  In case of broadcast enabled the corrections
+        aren't needed, as element size is always 32 or 64 bits.  */
+      if (!vex.b
+         && (bytemode == xmmq_mode
+             || bytemode == evex_half_bcst_xmmq_mode))
+       shift -= 1;
+      else if (bytemode == xmmqd_mode)
+       shift -= 2;
+      else if (bytemode == xmmdw_mode)
+       shift -= 3;
+      else if (bytemode == ymmq_mode && vex.length == 128)
+       shift -= 1;

     }
     }

-  oappend (names[reg]);
-}
-
-static void
-OP_E_memory (int bytemode, int sizeflag)
-{
-  bfd_vma disp = 0;
-  int add = (rex & REX_B) ? 8 : 0;
-  int riprel = 0;
+  else
+    shift = 0;

 
   USED_REX (REX_B);
   if (intel_syntax)
 
   USED_REX (REX_B);
   if (intel_syntax)


@@ -13114,6 +14869,11 @@ OP_E_memory (int bytemode, int sizeflag)
       int base, rbase;
       int vindex = 0;
       int scale = 0;
       int base, rbase;
       int vindex = 0;
       int scale = 0;

+      int addr32flag = !((sizeflag & AFLAG)
+                        || bytemode == v_bnd_mode
+                        || bytemode == bnd_mode);
+      const char **indexes64 = names64;
+      const char **indexes32 = names32;

 
       havesib = 0;
       havebase = 1;
 
       havesib = 0;
       havebase = 1;


@@ -13124,12 +14884,55 @@ OP_E_memory (int bytemode, int sizeflag)
        {
          havesib = 1;
          vindex = sib.index;
        {
          havesib = 1;
          vindex = sib.index;

-         scale = sib.scale;
-         base = sib.base;

          USED_REX (REX_X);
          if (rex & REX_X)
            vindex += 8;
          USED_REX (REX_X);
          if (rex & REX_X)
            vindex += 8;

-         haveindex = vindex != 4;
+         switch (bytemode)
+           {
+           case vex_vsib_d_w_dq_mode:
+           case vex_vsib_d_w_d_mode:
+           case vex_vsib_q_w_dq_mode:
+           case vex_vsib_q_w_d_mode:
+             if (!need_vex)
+               abort ();
+             if (vex.evex)
+               {
+                 if (!vex.v)
+                   vindex += 16;
+               }
+
+             haveindex = 1;
+             switch (vex.length)
+               {
+               case 128:
+                 indexes64 = indexes32 = names_xmm;
+                 break;
+               case 256:
+                 if (!vex.w
+                     || bytemode == vex_vsib_q_w_dq_mode
+                     || bytemode == vex_vsib_q_w_d_mode)
+                   indexes64 = indexes32 = names_ymm;
+                 else
+                   indexes64 = indexes32 = names_xmm;
+                 break;
+               case 512:
+                 if (!vex.w
+                     || bytemode == vex_vsib_q_w_dq_mode
+                     || bytemode == vex_vsib_q_w_d_mode)
+                   indexes64 = indexes32 = names_zmm;
+                 else
+                   indexes64 = indexes32 = names_ymm;
+                 break;
+               default:
+                 abort ();
+               }
+             break;
+           default:
+             haveindex = vindex != 4;
+             break;
+           }
+         scale = sib.scale;
+         base = sib.base;

          codep++;
        }
       rbase = base + add;
          codep++;
        }
       rbase = base + add;


@@ -13150,6 +14953,8 @@ OP_E_memory (int bytemode, int sizeflag)
          disp = *codep++;
          if ((disp & 0x80) != 0)
            disp -= 0x100;
          disp = *codep++;
          if ((disp & 0x80) != 0)
            disp -= 0x100;

+         if (vex.evex && shift > 0)
+           disp <<= shift;

          break;
        case 2:
          disp = get32s ();
          break;
        case 2:
          disp = get32s ();


@@ -13181,7 +14986,9 @@ OP_E_memory (int bytemode, int sizeflag)
              }
          }
 
              }
          }
 

-      if (havebase || haveindex || riprel)
+      if ((havebase || haveindex || riprel)
+         && (bytemode != v_bnd_mode)
+         && (bytemode != bnd_mode))

        used_prefixes |= PREFIX_ADDR;
 
       if (havedisp || (intel_syntax && riprel))
        used_prefixes |= PREFIX_ADDR;
 
       if (havedisp || (intel_syntax && riprel))


@@ -13194,7 +15001,7 @@ OP_E_memory (int bytemode, int sizeflag)
            }
          *obufp = '\0';
          if (havebase)
            }
          *obufp = '\0';
          if (havebase)

-           oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
+           oappend (address_mode == mode_64bit && !addr32flag

                     ? names64[rbase] : names32[rbase]);
          if (havesib)
            {
                     ? names64[rbase] : names32[rbase]);
          if (havesib)
            {


@@ -13211,12 +15018,10 @@ OP_E_memory (int bytemode, int sizeflag)
                      *obufp = '\0';
                    }
                  if (haveindex)
                      *obufp = '\0';
                    }
                  if (haveindex)

-                   oappend (address_mode == mode_64bit 
-                            && (sizeflag & AFLAG)
-                            ? names64[vindex] : names32[vindex]);
+                   oappend (address_mode == mode_64bit && !addr32flag
+                            ? indexes64[vindex] : indexes32[vindex]);

                  else
                  else

-                   oappend (address_mode == mode_64bit 
-                            && (sizeflag & AFLAG)
+                   oappend (address_mode == mode_64bit && !addr32flag

                             ? index64 : index32);
 
                  *obufp++ = scale_char;
                             ? index64 : index32);
 
                  *obufp++ = scale_char;


@@ -13254,10 +15059,7 @@ OP_E_memory (int bytemode, int sizeflag)
        {
          if (modrm.mod != 0 || base == 5)
            {
        {
          if (modrm.mod != 0 || base == 5)
            {

-             if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
-                             | PREFIX_ES | PREFIX_FS | PREFIX_GS))
-               ;
-             else
+             if (!active_seg_prefix)

                {
                  oappend (names_seg[ds_reg - es_reg]);
                  oappend (":");
                {
                  oappend (names_seg[ds_reg - es_reg]);
                  oappend (":");


@@ -13330,10 +15132,7 @@ OP_E_memory (int bytemode, int sizeflag)
        }
       else if (intel_syntax)
        {
        }
       else if (intel_syntax)
        {

-         if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
-                         | PREFIX_ES | PREFIX_FS | PREFIX_GS))
-           ;
-         else
+         if (!active_seg_prefix)

            {
              oappend (names_seg[ds_reg - es_reg]);
              oappend (":");
            {
              oappend (names_seg[ds_reg - es_reg]);
              oappend (":");


@@ -13342,6 +15141,48 @@ OP_E_memory (int bytemode, int sizeflag)
          oappend (scratchbuf);
        }
     }
          oappend (scratchbuf);
        }
     }

+  if (vex.evex && vex.b
+      && (bytemode == x_mode
+         || bytemode == xmmq_mode
+         || bytemode == evex_half_bcst_xmmq_mode))
+    {
+      if (vex.w
+         || bytemode == xmmq_mode
+         || bytemode == evex_half_bcst_xmmq_mode)
+       {
+         switch (vex.length)
+           {
+           case 128:
+             oappend ("{1to2}");
+             break;
+           case 256:
+             oappend ("{1to4}");
+             break;
+           case 512:
+             oappend ("{1to8}");
+             break;
+           default:
+             abort ();
+           }
+       }
+      else
+       {
+         switch (vex.length)
+           {
+           case 128:
+             oappend ("{1to4}");
+             break;
+           case 256:
+             oappend ("{1to8}");
+             break;
+           case 512:
+             oappend ("{1to16}");
+             break;
+           default:
+             abort ();
+           }
+       }
+    }

 }
 
 static void
 }
 
 static void


@@ -13377,16 +15218,22 @@ OP_G (int bytemode, int sizeflag)
       oappend (names16[modrm.reg + add]);
       break;
     case d_mode:
       oappend (names16[modrm.reg + add]);
       break;
     case d_mode:

+    case db_mode:
+    case dw_mode:

       oappend (names32[modrm.reg + add]);
       break;
     case q_mode:
       oappend (names64[modrm.reg + add]);
       break;
       oappend (names32[modrm.reg + add]);
       break;
     case q_mode:
       oappend (names64[modrm.reg + add]);
       break;

+    case bnd_mode:
+      oappend (names_bnd[modrm.reg]);
+      break;

     case v_mode:
     case dq_mode:
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:
     case v_mode:
     case dq_mode:
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:

+    case dqw_swap_mode:

       USED_REX (REX_W);
       if (rex & REX_W)
        oappend (names64[modrm.reg + add]);
       USED_REX (REX_W);
       if (rex & REX_W)
        oappend (names64[modrm.reg + add]);


@@ -13405,6 +15252,10 @@ OP_G (int bytemode, int sizeflag)
       else
        oappend (names32[modrm.reg + add]);
       break;
       else
        oappend (names32[modrm.reg + add]);
       break;

+    case mask_bd_mode:
+    case mask_mode:
+      oappend (names_mask[modrm.reg + add]);
+      break;

     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       break;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       break;


@@ -13498,6 +15349,15 @@ OP_REG (int code, int sizeflag)
 {
   const char *s;
   int add;
 {
   const char *s;
   int add;

+
+  switch (code)
+    {
+    case es_reg: case ss_reg: case cs_reg:
+    case ds_reg: case fs_reg: case gs_reg:
+      oappend (names_seg[code - es_reg]);
+      return;
+    }
+

   USED_REX (REX_B);
   if (rex & REX_B)
     add = 8;
   USED_REX (REX_B);
   if (rex & REX_B)
     add = 8;


@@ -13510,10 +15370,6 @@ OP_REG (int code, int sizeflag)
     case sp_reg: case bp_reg: case si_reg: case di_reg:
       s = names16[code - ax_reg + add];
       break;
     case sp_reg: case bp_reg: case si_reg: case di_reg:
       s = names16[code - ax_reg + add];
       break;

-    case es_reg: case ss_reg: case cs_reg:
-    case ds_reg: case fs_reg: case gs_reg:
-      s = names_seg[code - es_reg + add];
-      break;

     case al_reg: case ah_reg: case cl_reg: case ch_reg:
     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
       USED_REX (0);
     case al_reg: case ah_reg: case cl_reg: case ch_reg:
     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
       USED_REX (0);


@@ -13524,7 +15380,8 @@ OP_REG (int code, int sizeflag)
       break;
     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
       break;
     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:

-      if (address_mode == mode_64bit && (sizeflag & DFLAG))
+      if (address_mode == mode_64bit
+         && ((sizeflag & DFLAG) || (rex & REX_W)))

        {
          s = names64[code - rAX_reg + add];
          break;
        {
          s = names64[code - rAX_reg + add];
          break;


@@ -13655,7 +15512,7 @@ OP_I (int bytemode, int sizeflag)
       break;
     case const_1_mode:
       if (intel_syntax)
       break;
     case const_1_mode:
       if (intel_syntax)

-        oappend ("1");
+       oappend ("1");

       return;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);


@@ -13665,7 +15522,7 @@ OP_I (int bytemode, int sizeflag)
   op &= mask;
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);
   op &= mask;
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

   scratchbuf[0] = '\0';
 }
 
   scratchbuf[0] = '\0';
 }
 


@@ -13719,7 +15576,7 @@ OP_I64 (int bytemode, int sizeflag)
   op &= mask;
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);
   op &= mask;
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

   scratchbuf[0] = '\0';
 }
 
   scratchbuf[0] = '\0';
 }
 


@@ -13731,13 +15588,37 @@ OP_sI (int bytemode, int sizeflag)
   switch (bytemode)
     {
     case b_mode:
   switch (bytemode)
     {
     case b_mode:

+    case b_T_mode:

       FETCH_DATA (the_info, codep + 1);
       op = *codep++;
       if ((op & 0x80) != 0)
        op -= 0x100;
       FETCH_DATA (the_info, codep + 1);
       op = *codep++;
       if ((op & 0x80) != 0)
        op -= 0x100;

+      if (bytemode == b_T_mode)
+       {
+         if (address_mode != mode_64bit
+             || !((sizeflag & DFLAG) || (rex & REX_W)))
+           {
+             /* The operand-size prefix is overridden by a REX prefix.  */
+             if ((sizeflag & DFLAG) || (rex & REX_W))
+               op &= 0xffffffff;
+             else
+               op &= 0xffff;
+         }
+       }
+      else
+       {
+         if (!(rex & REX_W))
+           {
+             if (sizeflag & DFLAG)
+               op &= 0xffffffff;
+             else
+               op &= 0xffff;
+           }
+       }

       break;
     case v_mode:
       break;
     case v_mode:

-      if (sizeflag & DFLAG)
+      /* The operand-size prefix is overridden by a REX prefix.  */
+      if ((sizeflag & DFLAG) || (rex & REX_W))

        op = get32s ();
       else
        op = get16 ();
        op = get32s ();
       else
        op = get16 ();


@@ -13749,7 +15630,7 @@ OP_sI (int bytemode, int sizeflag)
 
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);
 
   scratchbuf[0] = '$';
   print_operand_value (scratchbuf + 1, 1, op);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

 }
 
 static void
 }
 
 static void


@@ -13792,7 +15673,7 @@ OP_J (int bytemode, int sizeflag)
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
     }
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
     }

-  disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
+  disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;

   set_op (disp, 0);
   print_operand_value (scratchbuf, 1, disp);
   oappend (scratchbuf);
   set_op (disp, 0);
   print_operand_value (scratchbuf, 1, disp);
   oappend (scratchbuf);


@@ -13846,8 +15727,7 @@ OP_OFF (int bytemode, int sizeflag)
 
   if (intel_syntax)
     {
 
   if (intel_syntax)
     {

-      if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
-                       | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
+      if (!active_seg_prefix)

        {
          oappend (names_seg[ds_reg - es_reg]);
          oappend (":");
        {
          oappend (names_seg[ds_reg - es_reg]);
          oappend (":");


@@ -13877,8 +15757,7 @@ OP_OFF64 (int bytemode, int sizeflag)
 
   if (intel_syntax)
     {
 
   if (intel_syntax)
     {

-      if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
-                       | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
+      if (!active_seg_prefix)

        {
          oappend (names_seg[ds_reg - es_reg]);
          oappend (":");
        {
          oappend (names_seg[ds_reg - es_reg]);
          oappend (":");


@@ -13931,7 +15810,7 @@ OP_ESreg (int code, int sizeflag)
          intel_operand_size (b_mode, sizeflag);
        }
     }
          intel_operand_size (b_mode, sizeflag);
        }
     }

-  oappend ("%es:" + intel_syntax);
+  oappend_maybe_intel ("%es:");

   ptr_reg (code, sizeflag);
 }
 
   ptr_reg (code, sizeflag);
 }
 


@@ -13954,14 +15833,10 @@ OP_DSreg (int code, int sizeflag)
          intel_operand_size (b_mode, sizeflag);
        }
     }
          intel_operand_size (b_mode, sizeflag);
        }
     }

-  if ((prefixes
-       & (PREFIX_CS
-         | PREFIX_DS
-         | PREFIX_SS
-         | PREFIX_ES
-         | PREFIX_FS
-         | PREFIX_GS)) == 0)
-    prefixes |= PREFIX_DS;
+  /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
+     default segment register DS is printed.  */
+  if (!active_seg_prefix)
+    active_seg_prefix = PREFIX_DS;

   append_seg ();
   ptr_reg (code, sizeflag);
 }
   append_seg ();
   ptr_reg (code, sizeflag);
 }


@@ -13984,7 +15859,7 @@ OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   else
     add = 0;
   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
   else
     add = 0;
   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

 }
 
 static void
 }
 
 static void


@@ -14007,16 +15882,16 @@ static void
 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {
   sprintf (scratchbuf, "%%tr%d", modrm.reg);
 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 {
   sprintf (scratchbuf, "%%tr%d", modrm.reg);

-  oappend (scratchbuf + intel_syntax);
+  oappend_maybe_intel (scratchbuf);

 }
 
 static void
 OP_R (int bytemode, int sizeflag)
 {
 }
 
 static void
 OP_R (int bytemode, int sizeflag)
 {

-  if (modrm.mod == 3)
-    OP_E (bytemode, sizeflag);
-  else
-    BadOp ();
+  /* Skip mod/rm byte.  */
+  MODRM_CHECK;
+  codep++;
+  OP_E_register (bytemode, sizeflag);

 }
 
 static void
 }
 
 static void


@@ -14047,8 +15922,17 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   USED_REX (REX_R);
   if (rex & REX_R)
     reg += 8;
   USED_REX (REX_R);
   if (rex & REX_R)
     reg += 8;

+  if (vex.evex)
+    {
+      if (!vex.r)
+       reg += 16;
+    }
+

   if (need_vex
       && bytemode != xmm_mode
   if (need_vex
       && bytemode != xmm_mode

+      && bytemode != xmmq_mode
+      && bytemode != evex_half_bcst_xmmq_mode
+      && bytemode != ymm_mode

       && bytemode != scalar_mode)
     {
       switch (vex.length)
       && bytemode != scalar_mode)
     {
       switch (vex.length)


@@ -14057,12 +15941,38 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
          names = names_xmm;
          break;
        case 256:
          names = names_xmm;
          break;
        case 256:

+         if (vex.w
+             || (bytemode != vex_vsib_q_w_dq_mode
+                 && bytemode != vex_vsib_q_w_d_mode))
+           names = names_ymm;
+         else
+           names = names_xmm;
+         break;
+       case 512:
+         names = names_zmm;
+         break;
+       default:
+         abort ();
+       }
+    }
+  else if (bytemode == xmmq_mode
+          || bytemode == evex_half_bcst_xmmq_mode)
+    {
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+         names = names_xmm;
+         break;
+       case 512:

          names = names_ymm;
          break;
        default:
          abort ();
        }
     }
          names = names_ymm;
          break;
        default:
          abort ();
        }
     }

+  else if (bytemode == ymm_mode)
+    names = names_ymm;

   else
     names = names_xmm;
   oappend (names[reg]);
   else
     names = names_xmm;
   oappend (names[reg]);


@@ -14081,7 +15991,7 @@ OP_EM (int bytemode, int sizeflag)
        {
          bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
          used_prefixes |= (prefixes & PREFIX_DATA);
        {
          bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
          used_prefixes |= (prefixes & PREFIX_DATA);

-       }
+       }

       OP_E (bytemode, sizeflag);
       return;
     }
       OP_E (bytemode, sizeflag);
       return;
     }


@@ -14120,7 +16030,7 @@ OP_EMC (int bytemode, int sizeflag)
        {
          bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
          used_prefixes |= (prefixes & PREFIX_DATA);
        {
          bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
          used_prefixes |= (prefixes & PREFIX_DATA);

-       }
+       }

       OP_E (bytemode, sizeflag);
       return;
     }
       OP_E (bytemode, sizeflag);
       return;
     }


@@ -14159,20 +16069,36 @@ OP_EX (int bytemode, int sizeflag)
   USED_REX (REX_B);
   if (rex & REX_B)
     reg += 8;
   USED_REX (REX_B);
   if (rex & REX_B)
     reg += 8;

+  if (vex.evex)
+    {
+      USED_REX (REX_X);
+      if ((rex & REX_X))
+       reg += 16;
+    }

 
   if ((sizeflag & SUFFIX_ALWAYS)
       && (bytemode == x_swap_mode
          || bytemode == d_swap_mode
 
   if ((sizeflag & SUFFIX_ALWAYS)
       && (bytemode == x_swap_mode
          || bytemode == d_swap_mode

-         || bytemode == d_scalar_swap_mode 
+         || bytemode == dqw_swap_mode
+         || bytemode == d_scalar_swap_mode

          || bytemode == q_swap_mode
          || bytemode == q_scalar_swap_mode))
     swap_operand ();
 
   if (need_vex
       && bytemode != xmm_mode
          || bytemode == q_swap_mode
          || bytemode == q_scalar_swap_mode))
     swap_operand ();
 
   if (need_vex
       && bytemode != xmm_mode

+      && bytemode != xmmdw_mode
+      && bytemode != xmmqd_mode
+      && bytemode != xmm_mb_mode
+      && bytemode != xmm_mw_mode
+      && bytemode != xmm_md_mode
+      && bytemode != xmm_mq_mode
+      && bytemode != xmm_mdq_mode

       && bytemode != xmmq_mode
       && bytemode != xmmq_mode

+      && bytemode != evex_half_bcst_xmmq_mode
+      && bytemode != ymm_mode

       && bytemode != d_scalar_mode
       && bytemode != d_scalar_mode

-      && bytemode != d_scalar_swap_mode 
+      && bytemode != d_scalar_swap_mode

       && bytemode != q_scalar_mode
       && bytemode != q_scalar_swap_mode
       && bytemode != vex_scalar_w_dq_mode)
       && bytemode != q_scalar_mode
       && bytemode != q_scalar_swap_mode
       && bytemode != vex_scalar_w_dq_mode)


@@ -14185,10 +16111,31 @@ OP_EX (int bytemode, int sizeflag)
        case 256:
          names = names_ymm;
          break;
        case 256:
          names = names_ymm;
          break;

+       case 512:
+         names = names_zmm;
+         break;
+       default:
+         abort ();
+       }
+    }
+  else if (bytemode == xmmq_mode
+          || bytemode == evex_half_bcst_xmmq_mode)
+    {
+      switch (vex.length)
+       {
+       case 128:
+       case 256:
+         names = names_xmm;
+         break;
+       case 512:
+         names = names_ymm;
+         break;

        default:
          abort ();
        }
     }
        default:
          abort ();
        }
     }

+  else if (bytemode == ymm_mode)
+    names = names_ymm;

   else
     names = names_xmm;
   oappend (names[reg]);
   else
     names = names_xmm;
   oappend (names[reg]);


@@ -14383,7 +16330,7 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, cmp_type);
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, cmp_type);

-      oappend (scratchbuf + intel_syntax);
+      oappend_maybe_intel (scratchbuf);

       scratchbuf[0] = '\0';
     }
 }
       scratchbuf[0] = '\0';
     }
 }


@@ -14473,6 +16420,67 @@ REP_Fixup (int bytemode, int sizeflag)
     }
 }
 
     }
 }
 

+/* For BND-prefixed instructions 0xF2 prefix should be displayed as
+   "bnd".  */
+
+static void
+BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (prefixes & PREFIX_REPNZ)
+    all_prefixes[last_repnz_prefix] = BND_PREFIX;
+}
+
+/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
+   "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
+ */
+
+static void
+HLE_Fixup1 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3
+      && (prefixes & PREFIX_LOCK) != 0)
+    {
+      if (prefixes & PREFIX_REPZ)
+       all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+       all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+
+  OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
+   "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
+ */
+
+static void
+HLE_Fixup2 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3)
+    {
+      if (prefixes & PREFIX_REPZ)
+       all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+       all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+
+  OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
+   "xrelease" for memory operand.  No check for LOCK prefix.   */
+
+static void
+HLE_Fixup3 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3
+      && last_repz_prefix > last_repnz_prefix
+      && (prefixes & PREFIX_REPZ) != 0)
+    all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+
+  OP_E (bytemode, sizeflag);
+}
+

 static void
 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
 {
 static void
 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
 {


@@ -14484,6 +16492,14 @@ CMPXCHG8B_Fixup (int bytemode, int sizeflag)
       mnemonicendp = stpcpy (p, "16b");
       bytemode = o_mode;
     }
       mnemonicendp = stpcpy (p, "16b");
       bytemode = o_mode;
     }

+  else if ((prefixes & PREFIX_LOCK) != 0)
+    {
+      if (prefixes & PREFIX_REPZ)
+       all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+       all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+

   OP_M (bytemode, sizeflag);
 }
 
   OP_M (bytemode, sizeflag);
 }
 


@@ -14532,7 +16548,7 @@ CRC32_Fixup (int bytemode, int sizeflag)
       USED_REX (REX_W);
       if (rex & REX_W)
        *p++ = 'q';
       USED_REX (REX_W);
       if (rex & REX_W)
        *p++ = 'q';

-      else 
+      else

        {
          if (sizeflag & DFLAG)
            *p++ = 'l';
        {
          if (sizeflag & DFLAG)
            *p++ = 'l';


@@ -14614,6 +16630,12 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
     return;
 
   reg = vex.register_specifier;
     return;
 
   reg = vex.register_specifier;

+  if (vex.evex)
+    {
+      if (!vex.v)
+       reg += 16;
+    }
+

   if (bytemode == vex_scalar_mode)
     {
       oappend (names_xmm[reg]);
   if (bytemode == vex_scalar_mode)
     {
       oappend (names_xmm[reg]);


@@ -14627,6 +16649,8 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
        {
        case vex_mode:
        case vex128_mode:
        {
        case vex_mode:
        case vex128_mode:

+       case vex_vsib_q_w_dq_mode:
+       case vex_vsib_q_w_d_mode:

          names = names_xmm;
          break;
        case dq_mode:
          names = names_xmm;
          break;
        case dq_mode:


@@ -14635,6 +16659,10 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
          else
            names = names32;
          break;
          else
            names = names32;
          break;

+       case mask_bd_mode:
+       case mask_mode:
+         names = names_mask;
+         break;

        default:
          abort ();
          return;
        default:
          abort ();
          return;


@@ -14645,13 +16673,23 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
        {
        case vex_mode:
        case vex256_mode:
        {
        case vex_mode:
        case vex256_mode:

+         names = names_ymm;
+         break;
+       case vex_vsib_q_w_dq_mode:
+       case vex_vsib_q_w_d_mode:
+         names = vex.w ? names_ymm : names_xmm;
+         break;
+       case mask_bd_mode:
+       case mask_mode:
+         names = names_mask;

          break;
        default:
          abort ();
          return;
        }
          break;
        default:
          abort ();
          return;
        }

-
-      names = names_ymm;
+      break;
+    case 512:
+      names = names_zmm;

       break;
     default:
       abort ();
       break;
     default:
       abort ();


@@ -14671,55 +16709,55 @@ get_vex_imm8 (int sizeflag, int opnum)
     {
       /* There are SIB/displacement bytes.  */
       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
     {
       /* There are SIB/displacement bytes.  */
       if ((sizeflag & AFLAG) || address_mode == mode_64bit)

-        {
+       {

          /* 32/64 bit address mode */
          /* 32/64 bit address mode */

-          int base = modrm.rm;
+         int base = modrm.rm;

 
          /* Check SIB byte.  */
 
          /* Check SIB byte.  */

-          if (base == 4)
-            {
-              FETCH_DATA (the_info, codep + 1);
-              base = *codep & 7;
-              /* When decoding the third source, don't increase
-                 bytes_before_imm as this has already been incremented
-                 by one in OP_E_memory while decoding the second
-                 source operand.  */
-              if (opnum == 0)
-                bytes_before_imm++;
-            }
-
-          /* Don't increase bytes_before_imm when decoding the third source,
-             it has already been incremented by OP_E_memory while decoding
-             the second source operand.  */
-          if (opnum == 0)
-            {
-              switch (modrm.mod)
-                {
-                  case 0:
-                    /* When modrm.rm == 5 or modrm.rm == 4 and base in
-                       SIB == 5, there is a 4 byte displacement.  */
-                    if (base != 5)
-                      /* No displacement. */
-                      break;
-                  case 2:
-                    /* 4 byte displacement.  */
-                    bytes_before_imm += 4;
-                    break;
-                  case 1:
-                    /* 1 byte displacement.  */
-                    bytes_before_imm++;
-                    break;
-                }
-            }
-        }
+         if (base == 4)
+           {
+             FETCH_DATA (the_info, codep + 1);
+             base = *codep & 7;
+             /* When decoding the third source, don't increase
+                bytes_before_imm as this has already been incremented
+                by one in OP_E_memory while decoding the second
+                source operand.  */
+             if (opnum == 0)
+               bytes_before_imm++;
+           }
+
+         /* Don't increase bytes_before_imm when decoding the third source,
+            it has already been incremented by OP_E_memory while decoding
+            the second source operand.  */
+         if (opnum == 0)
+           {
+             switch (modrm.mod)
+               {
+                 case 0:
+                   /* When modrm.rm == 5 or modrm.rm == 4 and base in
+                      SIB == 5, there is a 4 byte displacement.  */
+                   if (base != 5)
+                     /* No displacement. */
+                     break;
+                 case 2:
+                   /* 4 byte displacement.  */
+                   bytes_before_imm += 4;
+                   break;
+                 case 1:
+                   /* 1 byte displacement.  */
+                   bytes_before_imm++;
+                   break;
+               }
+           }
+       }

       else
        {
          /* 16 bit address mode */
       else
        {
          /* 16 bit address mode */

-          /* Don't increase bytes_before_imm when decoding the third source,
-             it has already been incremented by OP_E_memory while decoding
-             the second source operand.  */
-          if (opnum == 0)
-            {
+         /* Don't increase bytes_before_imm when decoding the third source,
+            it has already been incremented by OP_E_memory while decoding
+            the second source operand.  */
+         if (opnum == 0)
+           {

              switch (modrm.mod)
                {
                case 0:
              switch (modrm.mod)
                {
                case 0:


@@ -14821,7 +16859,7 @@ OP_EX_VexImmW (int bytemode, int sizeflag)
       /* Output the imm8 directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
       /* Output the imm8 directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);

-      oappend (scratchbuf + intel_syntax);
+      oappend_maybe_intel (scratchbuf);

       scratchbuf[0] = '\0';
       codep++;
     }
       scratchbuf[0] = '\0';
       codep++;
     }


@@ -15050,7 +17088,54 @@ VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, cmp_type);
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, cmp_type);

-      oappend (scratchbuf + intel_syntax);
+      oappend_maybe_intel (scratchbuf);
+      scratchbuf[0] = '\0';
+    }
+}
+
+static void
+VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
+            int sizeflag ATTRIBUTE_UNUSED)
+{
+  unsigned int cmp_type;
+
+  if (!vex.evex)
+    abort ();
+
+  FETCH_DATA (the_info, codep + 1);
+  cmp_type = *codep++ & 0xff;
+  /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
+     If it's the case, print suffix, otherwise - print the immediate.  */
+  if (cmp_type < ARRAY_SIZE (simd_cmp_op)
+      && cmp_type != 3
+      && cmp_type != 7)
+    {
+      char suffix [3];
+      char *p = mnemonicendp - 2;
+
+      /* vpcmp* can have both one- and two-lettered suffix.  */
+      if (p[0] == 'p')
+       {
+         p++;
+         suffix[0] = p[0];
+         suffix[1] = '\0';
+       }
+      else
+       {
+         suffix[0] = p[0];
+         suffix[1] = p[1];
+         suffix[2] = '\0';
+       }
+
+      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
+      mnemonicendp += simd_cmp_op[cmp_type].len;
+    }
+  else
+    {
+      /* We have a reserved extension byte.  Output it directly.  */
+      scratchbuf[0] = '$';
+      print_operand_value (scratchbuf + 1, 1, cmp_type);
+      oappend_maybe_intel (scratchbuf);

       scratchbuf[0] = '\0';
     }
 }
       scratchbuf[0] = '\0';
     }
 }


@@ -15081,7 +17166,7 @@ PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
       break;
     default:
       break;
       break;
     default:
       break;

-    } 
+    }

   if (pclmul_type < ARRAY_SIZE (pclmul_op))
     {
       char suffix [4];
   if (pclmul_type < ARRAY_SIZE (pclmul_op))
     {
       char suffix [4];


@@ -15098,7 +17183,7 @@ PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, pclmul_type);
       /* We have a reserved extension byte.  Output it directly.  */
       scratchbuf[0] = '$';
       print_operand_value (scratchbuf + 1, 1, pclmul_type);

-      oappend (scratchbuf + intel_syntax);
+      oappend_maybe_intel (scratchbuf);

       scratchbuf[0] = '\0';
     }
 }
       scratchbuf[0] = '\0';
     }
 }


@@ -15177,3 +17262,40 @@ OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
   oappend (names[vex.register_specifier]);
 }
 
   oappend (names[vex.register_specifier]);
 }
 

+static void
+OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (!vex.evex
+      || (bytemode != mask_mode && bytemode != mask_bd_mode))
+    abort ();
+
+  USED_REX (REX_R);
+  if ((rex & REX_R) != 0 || !vex.r)
+    {
+      BadOp ();
+      return;
+    }
+
+  oappend (names_mask [modrm.reg]);
+}
+
+static void
+OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (!vex.evex
+      || (bytemode != evex_rounding_mode
+         && bytemode != evex_sae_mode))
+    abort ();
+  if (modrm.mod == 3 && vex.b)
+    switch (bytemode)
+      {
+      case evex_rounding_mode:
+       oappend (names_rounding[vex.ll]);
+       break;
+      case evex_sae_mode:
+       oappend ("{sae}");
+       break;
+      default:
+       break;
+      }
+}