+ bfd_boolean warn_p = FALSE;
+
+ do
+ {
+ bfd_boolean invalid = FALSE;
+
+ opcode = &arc_table[i++];
+
+ if (!(opcode->cpu & isa_mask))
+ continue;
+
+ if (arc_opcode_len (opcode) != (int) insn_len)
+ continue;
+
+ if ((insn & opcode->mask) != opcode->opcode)
+ continue;
+
+ *has_limm = FALSE;
+
+ /* Possible candidate, check the operands. */
+ for (opidx = opcode->operands; *opidx; opidx++)
+ {
+ int value, limmind;
+ const struct arc_operand *operand = &arc_operands[*opidx];
+
+ if (operand->flags & ARC_OPERAND_FAKE)
+ continue;
+
+ if (operand->extract)
+ value = (*operand->extract) (insn, &invalid);
+ else
+ value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
+
+ /* Check for LIMM indicator. If it is there, then make sure
+ we pick the right format. */
+ limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
+ if (operand->flags & ARC_OPERAND_IR
+ && !(operand->flags & ARC_OPERAND_LIMM))
+ {
+ if ((value == 0x3E && insn_len == 4)
+ || (value == limmind && insn_len == 2))
+ {
+ invalid = TRUE;
+ break;
+ }
+ }
+
+ if (operand->flags & ARC_OPERAND_LIMM
+ && !(operand->flags & ARC_OPERAND_DUPLICATE))
+ *has_limm = TRUE;
+ }
+
+ /* Check the flags. */
+ for (flgidx = opcode->flags; *flgidx; flgidx++)
+ {
+ /* Get a valid flag class. */
+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+ const unsigned *flgopridx;
+ int foundA = 0, foundB = 0;
+ unsigned int value;
+
+ /* Check first the extensions. */
+ if (cl_flags->flag_class & F_CLASS_EXTEND)
+ {
+ value = (insn & 0x1F);
+ if (arcExtMap_condCodeName (value))
+ continue;
+ }
+
+ /* Check for the implicit flags. */
+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
+ continue;
+
+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+ {
+ const struct arc_flag_operand *flg_operand =
+ &arc_flag_operands[*flgopridx];
+
+ value = (insn >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
+ if (value == flg_operand->code)
+ foundA = 1;
+ if (value)
+ foundB = 1;
+ }
+
+ if (!foundA && foundB)
+ {
+ invalid = TRUE;
+ break;
+ }
+ }
+
+ if (invalid)
+ continue;
+
+ if (insn_len == 4
+ && overlaps)
+ {
+ warn_p = TRUE;
+ t_op = opcode;
+ if (skip_this_opcode (opcode))
+ continue;
+ }
+
+ /* The instruction is valid. */
+ return opcode;
+ }
+ while (opcode->mask);
+
+ if (warn_p)
+ {
+ info->fprintf_func (info->stream,
+ _("\nWarning: disassembly may be wrong due to "
+ "guessed opcode class choice.\n"
+ "Use -M<class[,class]> to select the correct "
+ "opcode class(es).\n\t\t\t\t"));
+ return t_op;
+ }
+
+ return NULL;
+}
+
+/* Find opcode for INSN, trying various different sources. The instruction
+ length in INSN_LEN will be updated if the instruction requires a LIMM
+ extension.
+
+ A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
+ initialised, ready to iterate over the operands of the found opcode. If
+ the found opcode requires a LIMM then the LIMM value will be loaded into a
+ field of ITER.
+
+ This function returns TRUE in almost all cases, FALSE is reserved to
+ indicate an error (failing to find an opcode is not an error) a returned
+ result of FALSE would indicate that the disassembler can't continue.
+
+ If no matching opcode is found then the returned result will be TRUE, the
+ value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
+ INSN_LEN will be unchanged.
+
+ If a matching opcode is found, then the returned result will be TRUE, the
+ opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
+ 4 if the instruction requires a LIMM, and the LIMM value will have been
+ loaded into a field of ITER. Finally, ITER will have been initialised so
+ that calls to OPERAND_ITERATOR_NEXT will iterate over the opcode's
+ operands. */
+
+static bfd_boolean
+find_format (bfd_vma memaddr,
+ unsigned long long insn,
+ unsigned int * insn_len,
+ unsigned isa_mask,
+ struct disassemble_info * info,
+ const struct arc_opcode ** opcode_result,
+ struct arc_operand_iterator * iter)
+{
+ const struct arc_opcode *opcode = NULL;
+ bfd_boolean needs_limm;
+ const extInstruction_t *einsn, *i;
+ unsigned limm = 0;
+ struct arc_disassemble_info *arc_infop = info->private_data;
+
+ /* First, try the extension instructions. */
+ if (*insn_len == 4)
+ {
+ einsn = arcExtMap_insn (OPCODE_32BIT_INSN (insn), insn);
+ for (i = einsn; (i != NULL) && (opcode == NULL); i = i->next)
+ {
+ const char *errmsg = NULL;
+
+ opcode = arcExtMap_genOpcode (i, isa_mask, &errmsg);
+ if (opcode == NULL)
+ {
+ (*info->fprintf_func) (info->stream, "\
+An error occured while generating the extension instruction operations");
+ *opcode_result = NULL;
+ return FALSE;
+ }
+
+ opcode = find_format_from_table (info, opcode, insn, *insn_len,
+ isa_mask, &needs_limm, FALSE);
+ }
+ }
+
+ /* Then, try finding the first match in the opcode table. */
+ if (opcode == NULL)
+ opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
+ isa_mask, &needs_limm, TRUE);
+
+ if (needs_limm && opcode != NULL)
+ {
+ bfd_byte buffer[4];
+ int status;
+
+ status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
+ 4, info);
+ if (status != 0)
+ {
+ opcode = NULL;
+ }
+ else
+ {
+ limm = ARRANGE_ENDIAN (info, buffer);
+ *insn_len += 4;
+ }
+ }
+
+ if (opcode != NULL)
+ {
+ iter->insn = insn;
+ iter->limm = limm;
+ iter->opcode = opcode;
+ iter->opidx = opcode->operands;
+ }
+
+ *opcode_result = opcode;
+
+ /* Update private data. */
+ arc_infop->opcode = opcode;
+ arc_infop->limm = (needs_limm) ? limm : 0;
+ arc_infop->limm_p = needs_limm;
+
+ return TRUE;
+}
+
+static void
+print_flags (const struct arc_opcode *opcode,
+ unsigned long long *insn,
+ struct disassemble_info *info)
+{
+ const unsigned char *flgidx;
+ unsigned int value;
+ struct arc_disassemble_info *arc_infop = info->private_data;
+
+ /* Now extract and print the flags. */
+ for (flgidx = opcode->flags; *flgidx; flgidx++)
+ {
+ /* Get a valid flag class. */
+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+ const unsigned *flgopridx;
+
+ /* Check first the extensions. */
+ if (cl_flags->flag_class & F_CLASS_EXTEND)
+ {
+ const char *name;
+ value = (insn[0] & 0x1F);
+
+ name = arcExtMap_condCodeName (value);
+ if (name)
+ {
+ (*info->fprintf_func) (info->stream, ".%s", name);
+ continue;
+ }
+ }
+
+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+ {
+ const struct arc_flag_operand *flg_operand =
+ &arc_flag_operands[*flgopridx];
+
+ /* Implicit flags are only used for the insn decoder. */
+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
+ {
+ if (cl_flags->flag_class & F_CLASS_COND)
+ arc_infop->condition_code = flg_operand->code;
+ else if (cl_flags->flag_class & F_CLASS_WB)
+ arc_infop->writeback_mode = flg_operand->code;
+ else if (cl_flags->flag_class & F_CLASS_ZZ)
+ info->data_size = flg_operand->code;
+ continue;
+ }
+
+ if (!flg_operand->favail)
+ continue;
+
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
+ if (value == flg_operand->code)
+ {
+ /* FIXME!: print correctly nt/t flag. */
+ if (!special_flag_p (opcode->name, flg_operand->name))
+ (*info->fprintf_func) (info->stream, ".");
+ else if (info->insn_type == dis_dref)
+ {
+ switch (flg_operand->name[0])
+ {
+ case 'b':
+ info->data_size = 1;
+ break;
+ case 'h':
+ case 'w':
+ info->data_size = 2;
+ break;
+ default:
+ info->data_size = 4;
+ break;
+ }
+ }
+ if (flg_operand->name[0] == 'd'
+ && flg_operand->name[1] == 0)
+ info->branch_delay_insns = 1;
+
+ /* Check if it is a conditional flag. */
+ if (cl_flags->flag_class & F_CLASS_COND)
+ {
+ if (info->insn_type == dis_jsr)
+ info->insn_type = dis_condjsr;
+ else if (info->insn_type == dis_branch)
+ info->insn_type = dis_condbranch;
+ arc_infop->condition_code = flg_operand->code;
+ }
+
+ /* Check for the write back modes. */
+ if (cl_flags->flag_class & F_CLASS_WB)
+ arc_infop->writeback_mode = flg_operand->code;
+
+ (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
+ }
+ }
+ }
+}
+
+static const char *
+get_auxreg (const struct arc_opcode *opcode,
+ int value,
+ unsigned isa_mask)
+{
+ const char *name;
+ unsigned int i;
+ const struct arc_aux_reg *auxr = &arc_aux_regs[0];
+
+ if (opcode->insn_class != AUXREG)
+ return NULL;
+
+ name = arcExtMap_auxRegName (value);
+ if (name)
+ return name;
+
+ for (i = 0; i < arc_num_aux_regs; i++, auxr++)
+ {
+ if (!(auxr->cpu & isa_mask))
+ continue;
+
+ if (auxr->subclass != NONE)
+ return NULL;
+
+ if (auxr->address == value)
+ return auxr->name;
+ }
+ return NULL;
+}
+
+/* Convert a value representing an address type to a string used to refer to
+ the address type in assembly code. */
+
+static const char *
+get_addrtype (int value)
+{
+ if (value < 0 || value > addrtypenames_max)
+ return addrtypeunknown;
+
+ return addrtypenames[value];
+}
+
+/* Calculate the instruction length for an instruction starting with MSB
+ and LSB, the most and least significant byte. The ISA_MASK is used to
+ filter the instructions considered to only those that are part of the
+ current architecture.
+
+ The instruction lengths are calculated from the ARC_OPCODE table, and
+ cached for later use. */
+
+static unsigned int
+arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
+{
+ bfd_byte major_opcode = msb >> 3;
+
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ /* The nps400 extension set requires this special casing of the
+ instruction length calculation. Right now this is not causing any
+ problems as none of the known extensions overlap in opcode space,
+ but, if they ever do then we might need to start carrying
+ information around in the elf about which extensions are in use. */
+ if (major_opcode == 0xb)
+ {
+ bfd_byte minor_opcode = lsb & 0x1f;
+
+ if (minor_opcode < 4)
+ return 6;
+ else if (minor_opcode == 0x10 || minor_opcode == 0x11)
+ return 8;
+ }
+ if (major_opcode == 0xa)
+ {
+ return 8;
+ }
+ /* Fall through. */
+ case bfd_mach_arc_arc600:
+ return (major_opcode > 0xb) ? 2 : 4;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ return (major_opcode > 0x7) ? 2 : 4;
+ break;
+
+ default:
+ abort ();
+ }
+}
+
+/* Extract and return the value of OPERAND from the instruction whose value
+ is held in the array INSN. */
+
+static int
+extract_operand_value (const struct arc_operand *operand,
+ unsigned long long insn,
+ unsigned limm)
+{
+ int value;
+
+ /* Read the limm operand, if required. */
+ if (operand->flags & ARC_OPERAND_LIMM)
+ /* The second part of the instruction value will have been loaded as
+ part of the find_format call made earlier. */
+ value = limm;
+ else
+ {
+ if (operand->extract)
+ value = (*operand->extract) (insn, (int *) NULL);
+ else
+ {
+ if (operand->flags & ARC_OPERAND_ALIGNED32)
+ {
+ value = (insn >> operand->shift)
+ & ((1 << (operand->bits - 2)) - 1);
+ value = value << 2;
+ }
+ else
+ {
+ value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
+ }
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ {
+ int signbit = 1 << (operand->bits - 1);
+ value = (value ^ signbit) - signbit;
+ }
+ }
+ }
+
+ return value;
+}
+
+/* Find the next operand, and the operands value from ITER. Return TRUE if
+ there is another operand, otherwise return FALSE. If there is an
+ operand returned then the operand is placed into OPERAND, and the value
+ into VALUE. If there is no operand returned then OPERAND and VALUE are
+ unchanged. */
+
+static bfd_boolean
+operand_iterator_next (struct arc_operand_iterator *iter,
+ const struct arc_operand **operand,
+ int *value)
+{
+ if (*iter->opidx == 0)
+ {
+ *operand = NULL;
+ return FALSE;
+ }
+
+ *operand = &arc_operands[*iter->opidx];
+ *value = extract_operand_value (*operand, iter->insn, iter->limm);
+ iter->opidx++;
+
+ return TRUE;
+}
+
+/* Helper for parsing the options. */
+
+static void
+parse_option (const char *option)
+{
+ if (disassembler_options_cmp (option, "dsp") == 0)
+ add_to_decodelist (DSP, NONE);
+
+ else if (disassembler_options_cmp (option, "spfp") == 0)
+ add_to_decodelist (FLOAT, SPX);
+
+ else if (disassembler_options_cmp (option, "dpfp") == 0)
+ add_to_decodelist (FLOAT, DPX);
+
+ else if (disassembler_options_cmp (option, "quarkse_em") == 0)
+ {
+ add_to_decodelist (FLOAT, DPX);
+ add_to_decodelist (FLOAT, SPX);
+ add_to_decodelist (FLOAT, QUARKSE1);
+ add_to_decodelist (FLOAT, QUARKSE2);
+ }
+
+ else if (disassembler_options_cmp (option, "fpuda") == 0)
+ add_to_decodelist (FLOAT, DPA);
+
+ else if (disassembler_options_cmp (option, "fpus") == 0)
+ {
+ add_to_decodelist (FLOAT, SP);
+ add_to_decodelist (FLOAT, CVT);
+ }
+
+ else if (disassembler_options_cmp (option, "fpud") == 0)
+ {
+ add_to_decodelist (FLOAT, DP);
+ add_to_decodelist (FLOAT, CVT);
+ }
+ else if (CONST_STRNEQ (option, "hex"))
+ print_hex = TRUE;
+ else
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
+}