Automatic date update in version.in

[platform/upstream/binutils.git] / opcodes / aarch64-dis.c

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index bbd5a3e..589fa84 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1,5 +1,5 @@
 /* aarch64-dis.c -- AArch64 disassembler.
 /* aarch64-dis.c -- AArch64 disassembler.

-   Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+   Copyright (C) 2009-2014 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.


@@ -24,12 +24,7 @@
 #include "libiberty.h"
 #include "opintl.h"
 #include "aarch64-dis.h"
 #include "libiberty.h"
 #include "opintl.h"
 #include "aarch64-dis.h"

-
-#if !defined(EMBEDDED_ENV)
-#define SYMTAB_AVAILABLE 1

 #include "elf-bfd.h"
 #include "elf-bfd.h"

-#include "elf/aarch64.h"
-#endif

 
 #define ERR_OK   0
 #define ERR_UND -1
 
 #define ERR_OK   0
 #define ERR_UND -1


@@ -125,7 +120,7 @@ parse_aarch64_dis_options (const char *options)
    N.B. the fields are required to be in such an order than the most signficant
    field for VALUE comes the first, e.g. the <index> in
     SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
    N.B. the fields are required to be in such an order than the most signficant
    field for VALUE comes the first, e.g. the <index> in
     SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]

-   is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+   is encoded in H:L:M in some cases, the fields H:L:M should be passed in

    the order of H, L, M.  */
 
 static inline aarch64_insn
    the order of H, L, M.  */
 
 static inline aarch64_insn


@@ -229,6 +224,17 @@ aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
   return 1;
 }
 
   return 1;
 }
 

+int
+aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
+                  const aarch64_insn code ATTRIBUTE_UNUSED,
+                  const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  assert (info->idx == 1
+         || info->idx ==3);
+  info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
+  return 1;
+}
+

 /* e.g. IC <ic_op>{, <Xt>}.  */
 int
 aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
 /* e.g. IC <ic_op>{, <Xt>}.  */
 int
 aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,


@@ -427,11 +433,17 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
       info->reglist.index = QSsize;
       break;
     case 0x1:
       info->reglist.index = QSsize;
       break;
     case 0x1:

+      if (QSsize & 0x1)
+       /* UND.  */
+       return 0;

       info->qualifier = AARCH64_OPND_QLF_S_H;
       /* Index encoded in "Q:S:size<1>".  */
       info->reglist.index = QSsize >> 1;
       break;
     case 0x2:
       info->qualifier = AARCH64_OPND_QLF_S_H;
       /* Index encoded in "Q:S:size<1>".  */
       info->reglist.index = QSsize >> 1;
       break;
     case 0x2:

+      if ((QSsize >> 1) & 0x1)
+       /* UND.  */
+       return 0;

       if ((QSsize & 0x1) == 0)
        {
          info->qualifier = AARCH64_OPND_QLF_S_S;
       if ((QSsize & 0x1) == 0)
        {
          info->qualifier = AARCH64_OPND_QLF_S_S;


@@ -440,12 +452,12 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
        }
       else
        {
        }
       else
        {

-         info->qualifier = AARCH64_OPND_QLF_S_D;
-         /* Index encoded in "Q".  */
-         info->reglist.index = QSsize >> 3;

          if (extract_field (FLD_S, code, 0))
            /* UND */
            return 0;
          if (extract_field (FLD_S, code, 0))
            /* UND */
            return 0;

+         info->qualifier = AARCH64_OPND_QLF_S_D;
+         /* Index encoded in "Q".  */
+         info->reglist.index = QSsize >> 3;

        }
       break;
     default:
        }
       break;
     default:


@@ -1359,6 +1371,13 @@ do_special_decoding (aarch64_inst *inst)
          && extract_field (FLD_N, inst->value, 0) != value)
        return 0;
     }
          && extract_field (FLD_N, inst->value, 0) != value)
        return 0;
     }

+  /* 'sf' field.  */
+  if (inst->opcode->flags & F_LSE_SZ)
+    {
+      idx = select_operand_for_sf_field_coding (inst->opcode);
+      value = extract_field (FLD_lse_sz, inst->value, 0);
+      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
+    }

   /* size:Q fields.  */
   if (inst->opcode->flags & F_SIZEQ)
     return decode_sizeq (inst);
   /* size:Q fields.  */
   if (inst->opcode->flags & F_SIZEQ)
     return decode_sizeq (inst);


@@ -1478,6 +1497,20 @@ convert_extr_to_ror (aarch64_inst *inst)
   return 0;
 }
 
   return 0;
 }
 

+/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
+     is equivalent to:
+   USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0.  */
+static int
+convert_shll_to_xtl (aarch64_inst *inst)
+{
+  if (inst->operands[2].imm.value == 0)
+    {
+      inst->operands[2].type = AARCH64_OPND_NIL;
+      return 1;
+    }
+  return 0;
+}
+

 /* Convert
      UBFM <Xd>, <Xn>, #<shift>, #63.
    to
 /* Convert
      UBFM <Xd>, <Xn>, #<shift>, #63.
    to


@@ -1592,12 +1625,14 @@ convert_ubfm_to_lsl (aarch64_inst *inst)
 
 /* CINC <Wd>, <Wn>, <cond>
      is equivalent to:
 
 /* CINC <Wd>, <Wn>, <cond>
      is equivalent to:

-   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>).  */
+   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
+     where <cond> is not AL or NV.  */

 
 static int
 convert_from_csel (aarch64_inst *inst)
 {
 
 static int
 convert_from_csel (aarch64_inst *inst)
 {

-  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
+      && (inst->operands[3].cond->value & 0xe) != 0xe)

     {
       copy_operand_info (inst, 2, 3);
       inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
     {
       copy_operand_info (inst, 2, 3);
       inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);


@@ -1609,13 +1644,15 @@ convert_from_csel (aarch64_inst *inst)
 
 /* CSET <Wd>, <cond>
      is equivalent to:
 
 /* CSET <Wd>, <cond>
      is equivalent to:

-   CSINC <Wd>, WZR, WZR, invert(<cond>).  */
+   CSINC <Wd>, WZR, WZR, invert(<cond>)
+     where <cond> is not AL or NV.  */

 
 static int
 convert_csinc_to_cset (aarch64_inst *inst)
 {
   if (inst->operands[1].reg.regno == 0x1f
 
 static int
 convert_csinc_to_cset (aarch64_inst *inst)
 {
   if (inst->operands[1].reg.regno == 0x1f

-      && inst->operands[2].reg.regno == 0x1f)
+      && inst->operands[2].reg.regno == 0x1f
+      && (inst->operands[3].cond->value & 0xe) != 0xe)

     {
       copy_operand_info (inst, 1, 3);
       inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
     {
       copy_operand_info (inst, 1, 3);
       inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);


@@ -1731,6 +1768,11 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
       return convert_movebitmask_to_mov (inst);
     case OP_ROR_IMM:
       return convert_extr_to_ror (inst);
       return convert_movebitmask_to_mov (inst);
     case OP_ROR_IMM:
       return convert_extr_to_ror (inst);

+    case OP_SXTL:
+    case OP_SXTL2:
+    case OP_UXTL:
+    case OP_UXTL2:
+      return convert_shll_to_xtl (inst);

     default:
       return 0;
     }
     default:
       return 0;
     }