-/* Descriptor Macros */
-#define XILINX_XC7Z007S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z007s" }
-
-#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z010" }
-
-#define XILINX_XC7Z012S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z012s" }
-
-#define XILINX_XC7Z014S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z014s" }
-
-#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z015" }
-
-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z020" }
-
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z030" }
-
-#define XILINX_XC7Z035_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z035" }
-
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z045" }
-
-#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z100" }
+/* Device Names */
+#define XILINX_XC7Z007S_NAME "7z007s"
+#define XILINX_XC7Z010_NAME "7z010"
+#define XILINX_XC7Z012S_NAME "7z012s"
+#define XILINX_XC7Z014S_NAME "7z014s"
+#define XILINX_XC7Z015_NAME "7z015"
+#define XILINX_XC7Z020_NAME "7z020"
+#define XILINX_XC7Z030_NAME "7z030"
+#define XILINX_XC7Z035_NAME "7z035"
+#define XILINX_XC7Z045_NAME "7z045"
+#define XILINX_XC7Z100_NAME "7z100"
+
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .fpga_size = XILINX_XC##name##_SIZE, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#else
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#endif