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global: Migrate CONFIG_STACKBASE to CFG
[platform/kernel/u-boot.git]
/
include
/
spartan2.h
diff --git
a/include/spartan2.h
b/include/spartan2.h
index
087a27d
..
618eddd
100644
(file)
--- a/
include/spartan2.h
+++ b/
include/spartan2.h
@@
-1,8
+1,7
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SPARTAN2_H_
*/
#ifndef _SPARTAN2_H_
@@
-10,37
+9,40
@@
#include <xilinx.h>
#include <xilinx.h>
-extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan2_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
/* Slave Parallel Implementation function table */
typedef struct {
-
X
ilinx_pre_fn pre;
-
X
ilinx_pgm_fn pgm;
-
X
ilinx_init_fn init;
-
X
ilinx_err_fn err;
-
X
ilinx_done_fn done;
-
X
ilinx_clk_fn clk;
-
X
ilinx_cs_fn cs;
-
X
ilinx_wr_fn wr;
-
X
ilinx_rdata_fn rdata;
-
X
ilinx_wdata_fn wdata;
-
X
ilinx_busy_fn busy;
-
X
ilinx_abort_fn abort;
-
X
ilinx_post_fn post;
-}
Xilinx_Spartan2_Slave_P
arallel_fns;
+
x
ilinx_pre_fn pre;
+
x
ilinx_pgm_fn pgm;
+
x
ilinx_init_fn init;
+
x
ilinx_err_fn err;
+
x
ilinx_done_fn done;
+
x
ilinx_clk_fn clk;
+
x
ilinx_cs_fn cs;
+
x
ilinx_wr_fn wr;
+
x
ilinx_rdata_fn rdata;
+
x
ilinx_wdata_fn wdata;
+
x
ilinx_busy_fn busy;
+
x
ilinx_abort_fn abort;
+
x
ilinx_post_fn post;
+}
xilinx_spartan2_slave_p
arallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_serial_fns;
+
+#if defined(CONFIG_FPGA_SPARTAN2)
+extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS &spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS NULL
+#endif
/* Device Image Sizes
*********************************************************************/
/* Device Image Sizes
*********************************************************************/
@@
-63,36
+65,47
@@
typedef struct {
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#endif /* _SPARTAN2_H_ */
#endif /* _SPARTAN2_H_ */