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Merge branch 'master' of git://git.denx.de/u-boot-net
[platform/kernel/u-boot.git]
/
include
/
sdhci.h
diff --git
a/include/sdhci.h
b/include/sdhci.h
index
7544b49
..
bef37df
100644
(file)
--- a/
include/sdhci.h
+++ b/
include/sdhci.h
@@
-1,9
+1,8
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Back ported to the 8xx platform (from the 8260 platform) by
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
* Back ported to the 8xx platform (from the 8260 platform) by
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
@@
-167,6
+166,11
@@
#define SDHCI_CAN_64BIT BIT(28)
#define SDHCI_CAPABILITIES_1 0x44
#define SDHCI_CAN_64BIT BIT(28)
#define SDHCI_CAPABILITIES_1 0x44
+#define SDHCI_SUPPORT_SDR50 0x00000001
+#define SDHCI_SUPPORT_SDR104 0x00000002
+#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_USE_SDR50_TUNING 0x00002000
+
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
@@
-213,8
+217,15
@@
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
/* to make gcc happy */
struct sdhci_host;
/* to make gcc happy */
struct sdhci_host;
@@
-235,7
+246,10
@@
struct sdhci_ops {
#endif
int (*get_cd)(struct sdhci_host *host);
void (*set_control_reg)(struct sdhci_host *host);
#endif
int (*get_cd)(struct sdhci_host *host);
void (*set_control_reg)(struct sdhci_host *host);
+ void (*set_ios_post)(struct sdhci_host *host);
void (*set_clock)(struct sdhci_host *host, u32 div);
void (*set_clock)(struct sdhci_host *host, u32 div);
+ int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+ void (*set_delay)(struct sdhci_host *host);
};
struct sdhci_host {
};
struct sdhci_host {
@@
-244,6
+258,7
@@
struct sdhci_host {
unsigned int quirks;
unsigned int host_caps;
unsigned int version;
unsigned int quirks;
unsigned int host_caps;
unsigned int version;
+ unsigned int max_clk; /* Maximum Base Clock frequency */
unsigned int clk_mul; /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
unsigned int clk_mul; /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
@@
-371,11
+386,11
@@
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
* @host: SDHCI host structure
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
* @host: SDHCI host structure
- * @
max_clk: Maximum supported clock speed
in HZ (0 for default)
- * @
min_clk: Minimum supported clock speed
in HZ (0 for default)
+ * @
f_max: Maximum supported clock frequency
in HZ (0 for default)
+ * @
f_min: Minimum supported clock frequency
in HZ (0 for default)
*/
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
*/
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
- u32
max_clk, u32 min_clk
);
+ u32
f_max, u32 f_min
);
/**
* sdhci_bind() - Set up a new MMC block device
/**
* sdhci_bind() - Set up a new MMC block device
@@
-401,14
+416,14
@@
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
* @host: SDHCI host structure
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
* @host: SDHCI host structure
- * @
max_clk: Maximum supported clock speed
in HZ (0 for default)
- * @
min_clk: Minimum supported clock speed
in HZ (0 for default)
+ * @
f_max: Maximum supported clock frequency
in HZ (0 for default)
+ * @
f_min: Minimum supported clock frequency
in HZ (0 for default)
* @return 0 if OK, -ve on error
*/
* @return 0 if OK, -ve on error
*/
-int add_sdhci(struct sdhci_host *host, u32
max_clk, u32 min_clk
);
+int add_sdhci(struct sdhci_host *host, u32
f_max, u32 f_min
);
#endif /* !CONFIG_BLK */
#endif /* !CONFIG_BLK */
-#ifdef CONFIG_DM_MMC
_OPS
+#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
extern const struct dm_mmc_ops sdhci_ops;
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
extern const struct dm_mmc_ops sdhci_ops;