+/*
+ * Configure which SDRAM/DDR/DDR2 controller is equipped
+ */
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+ defined(CONFIG_AP1000) || defined(CONFIG_ML2)
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
+#endif
+
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
+#endif
+
+#if defined(CONFIG_405EX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_NAND_NDFC
+#endif
+
+/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
+#if defined(CONFIG_405EX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+
+#define PLB_ARBITER_BASE 0x80
+
+#define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
+#define PLB0_ACR_PPM_MASK 0xF0000000
+#define PLB0_ACR_PPM_FIXED 0x00000000
+#define PLB0_ACR_PPM_FAIR 0xD0000000
+#define PLB0_ACR_HBU_MASK 0x08000000
+#define PLB0_ACR_HBU_DISABLED 0x00000000
+#define PLB0_ACR_HBU_ENABLED 0x08000000
+#define PLB0_ACR_RDP_MASK 0x06000000
+#define PLB0_ACR_RDP_DISABLED 0x00000000
+#define PLB0_ACR_RDP_2DEEP 0x02000000
+#define PLB0_ACR_RDP_3DEEP 0x04000000
+#define PLB0_ACR_RDP_4DEEP 0x06000000
+#define PLB0_ACR_WRP_MASK 0x01000000
+#define PLB0_ACR_WRP_DISABLED 0x00000000
+#define PLB0_ACR_WRP_2DEEP 0x01000000
+
+#define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
+#define PLB1_ACR_PPM_MASK 0xF0000000
+#define PLB1_ACR_PPM_FIXED 0x00000000
+#define PLB1_ACR_PPM_FAIR 0xD0000000
+#define PLB1_ACR_HBU_MASK 0x08000000
+#define PLB1_ACR_HBU_DISABLED 0x00000000
+#define PLB1_ACR_HBU_ENABLED 0x08000000
+#define PLB1_ACR_RDP_MASK 0x06000000
+#define PLB1_ACR_RDP_DISABLED 0x00000000
+#define PLB1_ACR_RDP_2DEEP 0x02000000
+#define PLB1_ACR_RDP_3DEEP 0x04000000
+#define PLB1_ACR_RDP_4DEEP 0x06000000
+#define PLB1_ACR_WRP_MASK 0x01000000
+#define PLB1_ACR_WRP_DISABLED 0x00000000
+#define PLB1_ACR_WRP_2DEEP 0x01000000
+
+#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
+