+
+#elif defined(CONFIG_MPC8313)
+/* SICRL bits - MPC8313 specific */
+#define SICRL_LBC 0x30000000
+#define SICRL_UART 0x0C000000
+#define SICRL_SPI_A 0x03000000
+#define SICRL_SPI_B 0x00C00000
+#define SICRL_SPI_C 0x00300000
+#define SICRL_SPI_D 0x000C0000
+#define SICRL_USBDR_11 0x00000C00
+#define SICRL_USBDR_10 0x00000800
+#define SICRL_USBDR_01 0x00000400
+#define SICRL_USBDR_00 0x00000000
+#define SICRL_ETSEC1_A 0x0000000C
+#define SICRL_ETSEC2_A 0x00000003
+
+/* SICRH bits - MPC8313 specific */
+#define SICRH_INTR_A 0x02000000
+#define SICRH_INTR_B 0x00C00000
+#define SICRH_IIC 0x00300000
+#define SICRH_ETSEC2_B 0x000C0000
+#define SICRH_ETSEC2_C 0x00030000
+#define SICRH_ETSEC2_D 0x0000C000
+#define SICRH_ETSEC2_E 0x00003000
+#define SICRH_ETSEC2_F 0x00000C00
+#define SICRH_ETSEC2_G 0x00000300
+#define SICRH_ETSEC1_B 0x00000080
+#define SICRH_ETSEC1_C 0x00000060
+#define SICRH_GTX1_DLY 0x00000008
+#define SICRH_GTX2_DLY 0x00000004
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+
+#elif defined(CONFIG_MPC8315)
+/* SICRL bits - MPC8315 specific */
+#define SICRL_DMA_CH0 0xc0000000
+#define SICRL_DMA_SPI 0x30000000
+#define SICRL_UART 0x0c000000
+#define SICRL_IRQ4 0x02000000
+#define SICRL_IRQ5 0x01800000
+#define SICRL_IRQ6_7 0x00400000
+#define SICRL_IIC1 0x00300000
+#define SICRL_TDM 0x000c0000
+#define SICRL_TDM_SHARED 0x00030000
+#define SICRL_PCI_A 0x0000c000
+#define SICRL_ELBC_A 0x00003000
+#define SICRL_ETSEC1_A 0x000000c0
+#define SICRL_ETSEC1_B 0x00000030
+#define SICRL_ETSEC1_C 0x0000000c
+#define SICRL_TSEXPOBI 0x00000001
+
+/* SICRH bits - MPC8315 specific */
+#define SICRH_GPIO_0 0xc0000000
+#define SICRH_GPIO_1 0x30000000
+#define SICRH_GPIO_2 0x0c000000
+#define SICRH_GPIO_3 0x03000000
+#define SICRH_GPIO_4 0x00c00000
+#define SICRH_GPIO_5 0x00300000
+#define SICRH_GPIO_6 0x000c0000
+#define SICRH_GPIO_7 0x00030000
+#define SICRH_GPIO_8 0x0000c000
+#define SICRH_GPIO_9 0x00003000
+#define SICRH_GPIO_10 0x00000c00
+#define SICRH_GPIO_11 0x00000300
+#define SICRH_ETSEC2_A 0x000000c0
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+
+#elif defined(CONFIG_MPC837x)
+/* SICRL bits - MPC837x specific */
+#define SICRL_USB_A 0xC0000000
+#define SICRL_USB_B 0x30000000
+#define SICRL_USB_B_SD 0x20000000
+#define SICRL_UART 0x0C000000
+#define SICRL_GPIO_A 0x02000000
+#define SICRL_GPIO_B 0x01000000
+#define SICRL_GPIO_C 0x00800000
+#define SICRL_GPIO_D 0x00400000
+#define SICRL_GPIO_E 0x00200000
+#define SICRL_GPIO_F 0x00180000
+#define SICRL_GPIO_G 0x00040000
+#define SICRL_GPIO_H 0x00020000
+#define SICRL_GPIO_I 0x00010000
+#define SICRL_GPIO_J 0x00008000
+#define SICRL_GPIO_K 0x00004000
+#define SICRL_GPIO_L 0x00003000
+#define SICRL_DMA_A 0x00000800
+#define SICRL_DMA_B 0x00000400
+#define SICRL_DMA_C 0x00000200
+#define SICRL_DMA_D 0x00000100
+#define SICRL_DMA_E 0x00000080
+#define SICRL_DMA_F 0x00000040
+#define SICRL_DMA_G 0x00000020
+#define SICRL_DMA_H 0x00000010
+#define SICRL_DMA_I 0x00000008
+#define SICRL_DMA_J 0x00000004
+#define SICRL_LDP_A 0x00000002
+#define SICRL_LDP_B 0x00000001
+
+/* SICRH bits - MPC837x specific */
+#define SICRH_DDR 0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TMR 0x00010000
+#define SICRH_GPIO2_A 0x00008000
+#define SICRH_GPIO2_B 0x00004000
+#define SICRH_GPIO2_C 0x00002000
+#define SICRH_GPIO2_D 0x00001000
+#define SICRH_GPIO2_E 0x00000C00
+#define SICRH_GPIO2_E_SD 0x00000800
+#define SICRH_GPIO2_F 0x00000300
+#define SICRH_GPIO2_G 0x000000C0
+#define SICRH_GPIO2_H 0x00000030
+#define SICRH_SPI 0x00000003
+#define SICRH_SPI_SD 0x00000001
+
+#elif defined(CONFIG_MPC8308)
+/* SICRL bits - MPC8308 specific */
+#define SICRL_SPI_PF0 (0 << 28)
+#define SICRL_SPI_PF1 (1 << 28)
+#define SICRL_SPI_PF3 (3 << 28)
+#define SICRL_UART_PF0 (0 << 26)
+#define SICRL_UART_PF1 (1 << 26)
+#define SICRL_UART_PF3 (3 << 26)
+#define SICRL_IRQ_PF0 (0 << 24)
+#define SICRL_IRQ_PF1 (1 << 24)
+#define SICRL_I2C2_PF0 (0 << 20)
+#define SICRL_I2C2_PF1 (1 << 20)
+#define SICRL_ETSEC1_TX_CLK (0 << 6)
+#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
+
+/* SICRH bits - MPC8308 specific */
+#define SICRH_ESDHC_A_SD (0 << 30)
+#define SICRH_ESDHC_A_GTM (1 << 30)
+#define SICRH_ESDHC_A_GPIO (3 << 30)
+#define SICRH_ESDHC_B_SD (0 << 28)
+#define SICRH_ESDHC_B_GTM (1 << 28)
+#define SICRH_ESDHC_B_GPIO (3 << 28)
+#define SICRH_ESDHC_C_SD (0 << 26)
+#define SICRH_ESDHC_C_GTM (1 << 26)
+#define SICRH_ESDHC_C_GPIO (3 << 26)
+#define SICRH_GPIO_A_GPIO (0 << 24)
+#define SICRH_GPIO_A_TSEC2 (1 << 24)
+#define SICRH_GPIO_B_GPIO (0 << 22)
+#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
+#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
+#define SICRH_IEEE1588_A_TMR (1 << 20)
+#define SICRH_IEEE1588_A_GPIO (3 << 20)
+#define SICRH_USB (1 << 18)
+#define SICRH_GTM_GTM (1 << 16)
+#define SICRH_GTM_GPIO (3 << 16)
+#define SICRH_IEEE1588_B_TMR (1 << 14)
+#define SICRH_IEEE1588_B_GPIO (3 << 14)
+#define SICRH_ETSEC2_CRS (1 << 12)
+#define SICRH_ETSEC2_GPIO (3 << 12)
+#define SICRH_GPIOSEL_0 (0 << 8)
+#define SICRH_GPIOSEL_1 (1 << 8)
+#define SICRH_TMROBI_V3P3 (0 << 4)
+#define SICRH_TMROBI_V2P5 (1 << 4)
+#define SICRH_TSOBI1_V3P3 (0 << 1)
+#define SICRH_TSOBI1_V2P5 (1 << 1)
+#define SICRH_TSOBI2_V3P3 (0 << 0)
+#define SICRH_TSOBI2_V2P5 (1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S (0 << (30-2))
+#define SICR_1_UART1_UART1RTS (1 << (30-2))
+#define SICR_1_I2C_I2C (0 << (30-4))
+#define SICR_1_I2C_CKSTOP (1 << (30-4))
+#define SICR_1_IRQ_A_IRQ (0 << (30-6))
+#define SICR_1_IRQ_A_MCP (1 << (30-6))
+#define SICR_1_IRQ_B_IRQ (0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
+#define SICR_1_GPIO_A_GPIO (0 << (30-10))
+#define SICR_1_GPIO_A_SD (2 << (30-10))
+#define SICR_1_GPIO_A_DDR (3 << (30-10))
+#define SICR_1_GPIO_B_GPIO (0 << (30-12))
+#define SICR_1_GPIO_B_SD (2 << (30-12))
+#define SICR_1_GPIO_B_QE (3 << (30-12))
+#define SICR_1_GPIO_C_GPIO (0 << (30-14))
+#define SICR_1_GPIO_C_CAN (1 << (30-14))
+#define SICR_1_GPIO_C_DDR (2 << (30-14))
+#define SICR_1_GPIO_C_LCS (3 << (30-14))
+#define SICR_1_GPIO_D_GPIO (0 << (30-16))
+#define SICR_1_GPIO_D_CAN (1 << (30-16))
+#define SICR_1_GPIO_D_DDR (2 << (30-16))
+#define SICR_1_GPIO_D_LCS (3 << (30-16))
+#define SICR_1_GPIO_E_GPIO (0 << (30-18))
+#define SICR_1_GPIO_E_CAN (1 << (30-18))
+#define SICR_1_GPIO_E_DDR (2 << (30-18))
+#define SICR_1_GPIO_E_LCS (3 << (30-18))
+#define SICR_1_GPIO_F_GPIO (0 << (30-20))
+#define SICR_1_GPIO_F_CAN (1 << (30-20))
+#define SICR_1_GPIO_F_CK (2 << (30-20))
+#define SICR_1_USB_A_USBDR (0 << (30-22))
+#define SICR_1_USB_A_UART2S (1 << (30-22))
+#define SICR_1_USB_B_USBDR (0 << (30-24))
+#define SICR_1_USB_B_UART2S (1 << (30-24))
+#define SICR_1_USB_B_UART2RTS (2 << (30-24))
+#define SICR_1_USB_C_USBDR (0 << (30-26))
+#define SICR_1_USB_C_QE_EXT (3 << (30-26))
+#define SICR_1_FEC1_FEC1 (0 << (30-28))
+#define SICR_1_FEC1_GTM (1 << (30-28))
+#define SICR_1_FEC1_GPIO (2 << (30-28))
+#define SICR_1_FEC2_FEC2 (0 << (30-30))
+#define SICR_1_FEC2_GTM (1 << (30-30))
+#define SICR_1_FEC2_GPIO (2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3 (0 << (30-0))
+#define SICR_2_FEC3_TMR (1 << (30-0))
+#define SICR_2_FEC3_GPIO (2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
+#define SICR_2_ELBC_A_LA (0 << (30-4))
+#define SICR_2_ELBC_B_LCLK (0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR (0 << (30-12))
+#define SICR_2_USB_D_GPIO (2 << (30-12))
+#define SICR_2_USB_D_QE_BRG (3 << (30-12))
+#define SICR_2_PCI_PCI (0 << (30-14))
+#define SICR_2_PCI_CPCI_HS (2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
+#define SICR_2_QUIESCE_B (0 << (30-24))
+