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powerpc/85xx: Refactor some defines out of corenet_ds.h
[platform/kernel/u-boot.git]
/
include
/
mpc83xx.h
diff --git
a/include/mpc83xx.h
b/include/mpc83xx.h
index
07e0e0b
..
8292018
100644
(file)
--- a/
include/mpc83xx.h
+++ b/
include/mpc83xx.h
@@
-694,14
+694,21
@@
/* SPMR - System PLL Mode Register
*/
#define SPMR_LBIUCM 0x80000000
/* SPMR - System PLL Mode Register
*/
#define SPMR_LBIUCM 0x80000000
+#define SPMR_LBIUCM_SHIFT 31
#define SPMR_DDRCM 0x40000000
#define SPMR_DDRCM 0x40000000
+#define SPMR_DDRCM_SHIFT 30
#define SPMR_SPMF 0x0F000000
#define SPMR_SPMF 0x0F000000
+#define SPMR_SPMF_SHIFT 24
#define SPMR_CKID 0x00800000
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000
#define SPMR_CKID 0x00800000
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000
+#define SPMR_COREPLL_SHIFT 16
#define SPMR_CEVCOD 0x000000C0
#define SPMR_CEVCOD 0x000000C0
+#define SPMR_CEVCOD_SHIFT 6
#define SPMR_CEPDF 0x00000020
#define SPMR_CEPDF 0x00000020
+#define SPMR_CEPDF_SHIFT 5
#define SPMR_CEPMF 0x0000001F
#define SPMR_CEPMF 0x0000001F
+#define SPMR_CEPMF_SHIFT 0
/* OCCR - Output Clock Control Register
*/
/* OCCR - Output Clock Control Register
*/
@@
-993,6
+1000,7
@@
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_HSE 0x00000008
#define SDRAM_CFG_BI 0x00000001
/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
#define SDRAM_CFG_BI 0x00000001
/* DDR_SDRAM_MODE - DDR SDRAM Mode Register