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cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family.
[platform/kernel/u-boot.git]
/
include
/
mpc83xx.h
diff --git
a/include/mpc83xx.h
b/include/mpc83xx.h
index
16b6c62
..
336c0ac
100644
(file)
--- a/
include/mpc83xx.h
+++ b/
include/mpc83xx.h
@@
-25,6
+25,7
@@
/* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
/* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
/* IMMRBAR - Internal Memory Register Base Address
*/
/* IMMRBAR - Internal Memory Register Base Address
*/
@@
-438,9
+439,9
@@
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
-#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
-#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
@@
-1217,7
+1218,7
@@
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
-#define FCR_CMD2_SHIFT 8
+#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
@@
-1241,8
+1242,8
@@
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
-#define LTESR_FCT 0x40000000
-#define LTESR_PAR 0x20000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
@@
-1269,4
+1270,9
@@
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
+#endif
+
#endif /* __MPC83XX_H__ */
#endif /* __MPC83XX_H__ */