-#define ESDHC_HOSTCAPBLT_VS18 0x04000000
-#define ESDHC_HOSTCAPBLT_VS30 0x02000000
-#define ESDHC_HOSTCAPBLT_VS33 0x01000000
-#define ESDHC_HOSTCAPBLT_SRS 0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
-#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+/* Auto CMD error status register / system control 2 register */
+#define EXECUTE_TUNING 0x00400000
+#define SMPCLKSEL 0x00800000
+#define UHSM_MASK 0x00070000
+#define UHSM_SDR104_HS200 0x00030000
+
+/* Host controller capabilities register */
+#define HOSTCAPBLT_VS18 0x04000000
+#define HOSTCAPBLT_VS30 0x02000000
+#define HOSTCAPBLT_VS33 0x01000000
+#define HOSTCAPBLT_SRS 0x00800000
+#define HOSTCAPBLT_DMAS 0x00400000
+#define HOSTCAPBLT_HSS 0x00200000
+
+/* Tuning block control register */
+#define TBCTL_TB_EN 0x00000004
+#define HS400_MODE 0x00000010
+#define HS400_WNDW_ADJUST 0x00000040
+
+/* SD clock control register */
+#define CMD_CLK_CTL 0x00008000
+
+/* SD timing control register */
+#define FLW_CTL_BG 0x00008000