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SPDX: Convert all of our single license tags to Linux Kernel style
[platform/kernel/u-boot.git]
/
include
/
fsl_ddr_sdram.h
diff --git
a/include/fsl_ddr_sdram.h
b/include/fsl_ddr_sdram.h
index
44ae7fb
..
56c9db2
100644
(file)
--- a/
include/fsl_ddr_sdram.h
+++ b/
include/fsl_ddr_sdram.h
@@
-1,7
+1,7
@@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
/*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
*/
#ifndef FSL_DDR_MEMCTL_H
*/
#ifndef FSL_DDR_MEMCTL_H
@@
-173,6
+173,7
@@
typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_V0PT9_EN 0x40000000
#define DDR_CDR1_ODT_SHIFT 17
#define DDR_CDR1_ODT_MASK 0x6
#define DDR_CDR2_ODT_MASK 0x1
#define DDR_CDR1_ODT_SHIFT 17
#define DDR_CDR1_ODT_MASK 0x6
#define DDR_CDR2_ODT_MASK 0x1
@@
-189,6
+190,13
@@
typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@
-292,7
+300,7
@@
typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_cdr2;
unsigned int err_disable;
unsigned int err_int_en;
unsigned int ddr_cdr2;
unsigned int err_disable;
unsigned int err_int_en;
- unsigned int debug[
32
];
+ unsigned int debug[
64
];
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
@@
-358,6
+366,7
@@
typedef struct memctl_options_s {
unsigned int quad_rank_present;
unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
unsigned int x4_en; /* enable x4 devices */
unsigned int quad_rank_present;
unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
unsigned int x4_en; /* enable x4 devices */
+ unsigned int package_3ds;
/* Global Timing Parameters */
unsigned int cas_latency_override;
/* Global Timing Parameters */
unsigned int cas_latency_override;
@@
-367,7
+376,8
@@
typedef struct memctl_options_s {
unsigned int additive_latency_override_value;
unsigned int clk_adjust; /* */
unsigned int additive_latency_override_value;
unsigned int clk_adjust; /* */
- unsigned int cpo_override;
+ unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
+ unsigned int cpo_sample; /* optimize debug_29[24:31] */
unsigned int write_data_delay; /* DQS adjust */
unsigned int cswl_override;
unsigned int write_data_delay; /* DQS adjust */
unsigned int cswl_override;
@@
-399,6
+409,7
@@
typedef struct memctl_options_s {
unsigned int rcw_override;
unsigned int rcw_1;
unsigned int rcw_2;
unsigned int rcw_override;
unsigned int rcw_1;
unsigned int rcw_2;
+ unsigned int rcw_3;
/* control register 1 */
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
/* control register 1 */
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
@@
-468,4
+479,12
@@
typedef struct fixed_ddr_parm{
int max_freq;
fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
int max_freq;
fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
+
+/**
+ * fsl_initdram() - Set up the SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsl_initdram(void);
+
#endif
#endif