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Merge branch 'master' of git://git.denx.de/u-boot-spi
[platform/kernel/u-boot.git]
/
include
/
dwmmc.h
diff --git
a/include/dwmmc.h
b/include/dwmmc.h
index
5b9602c
..
4ceda5e
100644
(file)
--- a/
include/dwmmc.h
+++ b/
include/dwmmc.h
@@
-1,8
+1,7
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012 SAMSUNG Electronics
* Jaehoon Chung <jh80.chung@samsung.com>
/*
* (C) Copyright 2012 SAMSUNG Electronics
* Jaehoon Chung <jh80.chung@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DWMMC_HW_H
*/
#ifndef __DWMMC_HW_H
@@
-57,6
+56,7
@@
#define DWMCI_INTMSK_DTO (1 << 3)
#define DWMCI_INTMSK_TXDR (1 << 4)
#define DWMCI_INTMSK_RXDR (1 << 5)
#define DWMCI_INTMSK_DTO (1 << 3)
#define DWMCI_INTMSK_TXDR (1 << 4)
#define DWMCI_INTMSK_RXDR (1 << 5)
+#define DWMCI_INTMSK_RCRC (1 << 6)
#define DWMCI_INTMSK_DCRC (1 << 7)
#define DWMCI_INTMSK_RTO (1 << 8)
#define DWMCI_INTMSK_DRTO (1 << 9)
#define DWMCI_INTMSK_DCRC (1 << 7)
#define DWMCI_INTMSK_RTO (1 << 8)
#define DWMCI_INTMSK_DRTO (1 << 9)
@@
-104,6
+104,8
@@
#define DWMCI_CTYPE_8BIT (1 << 16)
/* Status Register */
#define DWMCI_CTYPE_8BIT (1 << 16)
/* Status Register */
+#define DWMCI_FIFO_EMPTY (1 << 2)
+#define DWMCI_FIFO_FULL (1 << 3)
#define DWMCI_BUSY (1 << 9)
#define DWMCI_FIFO_MASK 0x1fff
#define DWMCI_FIFO_SHIFT 17
#define DWMCI_BUSY (1 << 9)
#define DWMCI_FIFO_MASK 0x1fff
#define DWMCI_FIFO_SHIFT 17
@@
-253,14
+255,12
@@
static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
* See rockchip_dw_mmc.c for an example.
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
* See rockchip_dw_mmc.c for an example.
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
- * @name: Device name (normally dev->name)
- * @buswidth: Bus width (in bits, such as 4 or 8)
- * @caps: Host capabilities (MMC_MODE_...)
+ * @host: DWMMC host
* @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
* @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
*/
* @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
* @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
*/
-void dwmci_setup_cfg(struct mmc_config *cfg,
const char *name, int buswidth
,
-
uint caps,
u32 max_clk, u32 min_clk);
+void dwmci_setup_cfg(struct mmc_config *cfg,
struct dwmci_host *host
,
+ u32 max_clk, u32 min_clk);
/**
* dwmci_bind() - Set up a new MMC block device
/**
* dwmci_bind() - Set up a new MMC block device
@@
-293,7
+293,7
@@
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* !CONFIG_BLK */
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* !CONFIG_BLK */
-#ifdef CONFIG_DM_MMC
_OPS
+#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int dwmci_probe(struct udevice *dev);
extern const struct dm_mmc_ops dm_dwmci_ops;
/* Export the operations to drivers */
int dwmci_probe(struct udevice *dev);
extern const struct dm_mmc_ops dm_dwmci_ops;