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Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
[platform/kernel/u-boot.git]
/
include
/
configs
/
zylonite.h
diff --git
a/include/configs/zylonite.h
b/include/configs/zylonite.h
index
6febeea
..
86b6ea1
100644
(file)
--- a/
include/configs/zylonite.h
+++ b/
include/configs/zylonite.h
@@
-47,6
+47,9
@@
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
/*
* Size of malloc() pool
*/
/*
* Size of malloc() pool
*/
@@
-69,6
+72,7
@@
/*
* select serial console configuration
*/
/*
* select serial console configuration
*/
+#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_FFUART 1
/* allow to overwrite serial and ethaddr */
@@
-139,8
+143,6
@@
#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
#define CONFIG_SYS_HZ 1000
@@
-191,7
+193,6
@@
/*
* NAND Flash
*/
/*
* NAND Flash
*/
-#define CONFIG_NEW_NAND_CODE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
@@
-204,6
+205,8
@@
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
@@
-225,13
+228,6
@@
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1