-#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
-#define CFG_OR1_PRELIM 0xfc000a00
-#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
-#define CFG_OR2_PRELIM 0xfff00d24
-#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
-#define CFG_OR3_PRELIM 0xffff8f44
-#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
-#define CFG_OR4_PRELIM 0xffff0300
-#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
-#define CFG_OR5_PRELIM 0xffff8db0
+#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
+#define CONFIG_SYS_OR1_PRELIM 0xfc000a00
+#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
+#define CONFIG_SYS_OR2_PRELIM 0xfff00d24
+#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
+#define CONFIG_SYS_OR3_PRELIM 0xffff8f44
+#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
+#define CONFIG_SYS_OR4_PRELIM 0xffff0300
+#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
+#define CONFIG_SYS_OR5_PRELIM 0xffff8db0