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configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs
[platform/kernel/u-boot.git]
/
include
/
configs
/
theadorable.h
diff --git
a/include/configs/theadorable.h
b/include/configs/theadorable.h
index
e4ec2c0
..
85ab34c
100644
(file)
--- a/
include/configs/theadorable.h
+++ b/
include/configs/theadorable.h
@@
-1,7
+1,6
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
/*
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_THEADORABLE_H
*/
#ifndef _CONFIG_THEADORABLE_H
@@
-10,7
+9,6
@@
/*
* High Level Configuration Options (easy to change)
*/
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
@@
-20,10
+18,6
@@
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
- * Commands configuration
- */
-
-/*
* The debugging version enables USB support via defconfig.
* This version should also enable all other non-production
* interfaces / features.
* The debugging version enables USB support via defconfig.
* This version should also enable all other non-production
* interfaces / features.
@@
-41,22
+35,10
@@
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-
/* Environment in SPI NOR flash */
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PREBOOT
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@
-66,16
+48,13
@@
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
-/* PCIe support */
-#ifdef CONFIG_CMD_PCI
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#endif
-#endif
-
/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+
/* FPGA programming support */
#define CONFIG_FPGA_STRATIX_V
/* FPGA programming support */
#define CONFIG_FPGA_STRATIX_V
@@
-106,7
+85,6
@@
/* SPL */
/* Defines for SPL */
/* SPL */
/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
@@
-120,8
+98,6
@@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */