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Merge branch 'next'
[platform/kernel/u-boot.git]
/
include
/
configs
/
stxxtc.h
diff --git
a/include/configs/stxxtc.h
b/include/configs/stxxtc.h
index
3ffe6b2
..
5a5f772
100644
(file)
--- a/
include/configs/stxxtc.h
+++ b/
include/configs/stxxtc.h
@@
-63,35
+63,45
@@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_AUTOSCRIPT
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
"bootm"
#define CONFIG_AUTOSCRIPT
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#undef C
FG_LOADS_BAUD_CHANGE
/* don't allow baudrate change */
+#undef C
ONFIG_SYS_LOADS_BAUD_CHANGE
/* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#define FEC_ENET 1 /* eth.c needs it that way... */
-#undef C
FG
_DISCOVER_PHY
+#undef C
ONFIG_SYS
_DISCOVER_PHY
#define CONFIG_MII 1
#define CONFIG_MII 1
+#define CONFIG_MII_INIT 1
#undef CONFIG_RMII
#define CONFIG_ETHER_ON_FEC1 1
#undef CONFIG_RMII
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
+#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
#undef CONFIG_FEC1_PHY_NORXERR
#define CONFIG_ETHER_ON_FEC2 1
#undef CONFIG_FEC1_PHY_NORXERR
#define CONFIG_ETHER_ON_FEC2 1
@@
-100,45
+110,48
@@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_NFS)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
/*
* Miscellaneous configurable options
*/
-#define C
FG_LONGHELP
/* undef to save memory */
-#define C
FG_PROMPT
"xtc> " /* Monitor Command Prompt */
+#define C
ONFIG_SYS_LONGHELP
/* undef to save memory */
+#define C
ONFIG_SYS_PROMPT
"xtc> " /* Monitor Command Prompt */
-#define C
FG_HUSH_PARSER
1
-#define C
FG_PROMPT_HUSH_PS2
"> "
+#define C
ONFIG_SYS_HUSH_PARSER
1
+#define C
ONFIG_SYS_PROMPT_HUSH_PS2
"> "
-#if
(CONFIG_COMMANDS & CF
G_CMD_KGDB)
-#define C
FG_CBSIZE
1024 /* Console I/O Buffer Size */
+#if
defined(CONFI
G_CMD_KGDB)
+#define C
ONFIG_SYS_CBSIZE
1024 /* Console I/O Buffer Size */
#else
#else
-#define C
FG_CBSIZE
256 /* Console I/O Buffer Size */
+#define C
ONFIG_SYS_CBSIZE
256 /* Console I/O Buffer Size */
#endif
#endif
-#define C
FG_PBSIZE (CFG_CBSIZE+sizeof(CFG
_PROMPT)+16) /* Print Buffer Size */
-#define C
FG_MAXARGS
16 /* max number of command args */
-#define C
FG_BARGSIZE CFG_CBSIZE
/* Boot Argument Buffer Size */
+#define C
ONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS
_PROMPT)+16) /* Print Buffer Size */
+#define C
ONFIG_SYS_MAXARGS
16 /* max number of command args */
+#define C
ONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot Argument Buffer Size */
-#define C
FG_MEMTEST_START
0x0300000 /* memtest works on */
-#define C
FG_MEMTEST_END
0x0700000 /* 3 ... 7 MB in DRAM */
+#define C
ONFIG_SYS_MEMTEST_START
0x0300000 /* memtest works on */
+#define C
ONFIG_SYS_MEMTEST_END
0x0700000 /* 3 ... 7 MB in DRAM */
-#define C
FG_LOAD_ADDR
0x100000 /* default load address */
+#define C
ONFIG_SYS_LOAD_ADDR
0x100000 /* default load address */
-#define C
FG_HZ
1000 /* decrementer freq: 1 ms ticks */
+#define C
ONFIG_SYS_HZ
1000 /* decrementer freq: 1 ms ticks */
-#define C
FG_BAUDRATE_TABLE
{ 9600, 19200, 38400, 57600, 115200 }
+#define C
ONFIG_SYS_BAUDRATE_TABLE
{ 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
/*
* Low Level Configuration Settings
@@
-148,73
+161,73
@@
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define C
FG_IMMR
0xFF000000
+#define C
ONFIG_SYS_IMMR
0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define C
FG_INIT_RAM_ADDR CFG
_IMMR
-#define C
FG_INIT_RAM_END
0x3000 /* End of used area in DPRAM */
-#define C
FG_GBL_DATA_SIZE
64 /* size in bytes reserved for initial data */
-#define C
FG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG
_GBL_DATA_SIZE)
-#define C
FG_INIT_SP_OFFSET CFG
_GBL_DATA_OFFSET
+#define C
ONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS
_IMMR
+#define C
ONFIG_SYS_INIT_RAM_END
0x3000 /* End of used area in DPRAM */
+#define C
ONFIG_SYS_GBL_DATA_SIZE
64 /* size in bytes reserved for initial data */
+#define C
ONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS
_GBL_DATA_SIZE)
+#define C
ONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS
_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that C
FG
_SDRAM_BASE _must_ start at 0
+ * Please note that C
ONFIG_SYS
_SDRAM_BASE _must_ start at 0
*/
*/
-#define C
FG_SDRAM_BASE
0x00000000
-#define C
FG_FLASH_BASE
0x40000000
+#define C
ONFIG_SYS_SDRAM_BASE
0x00000000
+#define C
ONFIG_SYS_FLASH_BASE
0x40000000
#if defined(DEBUG)
#if defined(DEBUG)
-#define C
FG_MONITOR_LEN
(256 << 10) /* Reserve 256 kB for Monitor */
+#define C
ONFIG_SYS_MONITOR_LEN
(256 << 10) /* Reserve 256 kB for Monitor */
#else
#else
-#define C
FG_MONITOR_LEN
(192 << 10) /* Reserve 192 kB for Monitor */
+#define C
ONFIG_SYS_MONITOR_LEN
(192 << 10) /* Reserve 192 kB for Monitor */
#endif
/* yes this is weird, I know :) */
#endif
/* yes this is weird, I know :) */
-#define C
FG_MONITOR_BASE (CFG
_FLASH_BASE | 0x00F00000)
-#define C
FG_MALLOC_LEN
(128 << 10) /* Reserve 128 kB for malloc() */
+#define C
ONFIG_SYS_MONITOR_BASE (CONFIG_SYS
_FLASH_BASE | 0x00F00000)
+#define C
ONFIG_SYS_MALLOC_LEN
(128 << 10) /* Reserve 128 kB for malloc() */
-#define C
FG_RESET_ADDRESS
0x80000000
+#define C
ONFIG_SYS_RESET_ADDRESS
0x80000000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define C
FG_BOOTMAPSZ
(8 << 20) /* Initial Memory map for Linux */
+#define C
ONFIG_SYS_BOOTMAPSZ
(8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define C
FG_ENV_IS_IN_FLASH
1
-#define C
FG_ENV_SECT_SIZE
0x10000
+#define C
ONFIG_ENV_IS_IN_FLASH
1
+#define C
ONFIG_ENV_SECT_SIZE
0x10000
-#define C
FG_ENV_ADDR (CFG
_FLASH_BASE + 0x00000000)
-#define C
FG_ENV_OFFSET
0
-#define C
FG_ENV_SIZE
0x4000
+#define C
ONFIG_ENV_ADDR (CONFIG_SYS
_FLASH_BASE + 0x00000000)
+#define C
ONFIG_ENV_OFFSET
0
+#define C
ONFIG_ENV_SIZE
0x4000
-#define C
FG_ENV_ADDR_REDUND (CFG
_FLASH_BASE + 0x00010000)
-#define C
FG_ENV_OFFSET_REDUND
0
-#define C
FG_ENV_SIZE_REDUND CF
G_ENV_SIZE
+#define C
ONFIG_ENV_ADDR_REDUND (CONFIG_SYS
_FLASH_BASE + 0x00010000)
+#define C
ONFIG_ENV_OFFSET_REDUND
0
+#define C
ONFIG_ENV_SIZE_REDUND CONFI
G_ENV_SIZE
-#define C
FG_FLASH_CFI
1
-#define C
FG_FLASH_CFI_DRIVER
1
-#undef C
FG_FLASH_USE_BUFFER_WRITE
/* use buffered writes (20x faster) */
-#define C
FG_MAX_FLASH_SECT
128 /* max number of sectors on one chip */
-#define C
FG_MAX_FLASH_BANKS
2 /* max number of memory banks */
+#define C
ONFIG_SYS_FLASH_CFI
1
+#define C
ONFIG_FLASH_CFI_DRIVER
1
+#undef C
ONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* use buffered writes (20x faster) */
+#define C
ONFIG_SYS_MAX_FLASH_SECT
128 /* max number of sectors on one chip */
+#define C
ONFIG_SYS_MAX_FLASH_BANKS
2 /* max number of memory banks */
-#define C
FG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG
_FLASH_BASE + 0x2000000 }
+#define C
ONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE + 0x2000000 }
-#define C
FG
_FLASH_PROTECTION
+#define C
ONFIG_SYS
_FLASH_PROTECTION
/*-----------------------------------------------------------------------
* Cache Configuration
*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define C
FG_CACHELINE_SIZE
16 /* For all MPC8xx CPUs */
-#if
(CONFIG_COMMANDS & CF
G_CMD_KGDB)
-#define C
FG_CACHELINE_SHIFT
4 /* log base 2 of the above value */
+#define C
ONFIG_SYS_CACHELINE_SIZE
16 /* For all MPC8xx CPUs */
+#if
defined(CONFI
G_CMD_KGDB)
+#define C
ONFIG_SYS_CACHELINE_SHIFT
4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
#endif
/*-----------------------------------------------------------------------
@@
-224,10
+237,10
@@
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-#define C
FG_SYPCR
(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define C
ONFIG_SYS_SYPCR
(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
-#define C
FG_SYPCR
(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define C
ONFIG_SYS_SYPCR
(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
#endif
/*-----------------------------------------------------------------------
@@
-235,27
+248,27
@@
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#define C
FG_SIUMCR
(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+#define C
ONFIG_SYS_SIUMCR
(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
-#define C
FG_TBSCR
(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define C
ONFIG_SYS_TBSCR
(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
-#define C
FG_RTCSC
(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define C
ONFIG_SYS_RTCSC
(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
-#define C
FG_PISCR
(PISCR_PS | PISCR_PITF)
+#define C
ONFIG_SYS_PISCR
(PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
@@
-268,13
+281,13
@@
#if CONFIG_XIN == 10000000
#if MPC8XX_HZ == 50000000
#if CONFIG_XIN == 10000000
#if MPC8XX_HZ == 50000000
-#define C
FG_PLPRCR
((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define C
ONFIG_SYS_PLPRCR
((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#elif MPC8XX_HZ == 66666666
-#define C
FG_PLPRCR
((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+#define C
ONFIG_SYS_PLPRCR
((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
@@
-295,12
+308,12
@@
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
-#define C
FG_SCCR
(/* SCCR_TBS | */ SCCR_CRQEN | \
+#define C
ONFIG_SYS_SCCR
(/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
-#define C
FG_SCCR
(/* SCCR_TBS | */ SCCR_CRQEN | \
+#define C
ONFIG_SYS_SCCR
(/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
@@
-311,8
+324,8
@@
*-----------------------------------------------------------------------
*
*/
*-----------------------------------------------------------------------
*
*/
-/*#define C
FG_DER
0x2002000F*/
-#define C
FG_DER
0
+/*#define C
ONFIG_SYS_DER
0x2002000F*/
+#define C
ONFIG_SYS_DER
0
/*
* Init Memory Controller:
/*
* Init Memory Controller:
@@
-330,18
+343,18
@@
#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
-#define C
FG_REMAP_OR_AM
0x80000000
-#define C
FG_PRELIM_OR_AM
(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+#define C
ONFIG_SYS_REMAP_OR_AM
0x80000000
+#define C
ONFIG_SYS_PRELIM_OR_AM
(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define C
FG_OR_TIMING_FLASH
(OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define C
ONFIG_SYS_OR_TIMING_FLASH
(OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-#define C
FG_OR0_REMAP (CFG_REMAP_OR_AM | CFG
_OR_TIMING_FLASH)
-#define C
FG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG
_OR_TIMING_FLASH)
-#define C
FG_BR0_PRELIM
((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define C
ONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS
_OR_TIMING_FLASH)
+#define C
ONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS
_OR_TIMING_FLASH)
+#define C
ONFIG_SYS_BR0_PRELIM
((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#define C
FG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG
_OR_TIMING_FLASH)
-#define C
FG_BR1_PRELIM
((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define C
ONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS
_OR_TIMING_FLASH)
+#define C
ONFIG_SYS_BR1_PRELIM
((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
/*
* BR4 and OR4 (SDRAM)
/*
* BR4 and OR4 (SDRAM)
@@
-351,10
+364,10
@@
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define C
FG_OR_TIMING_SDRAM
(OR_CSNT_SAM | OR_G5LS)
+#define C
ONFIG_SYS_OR_TIMING_SDRAM
(OR_CSNT_SAM | OR_G5LS)
-#define C
FG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG
_OR_TIMING_SDRAM)
-#define C
FG_BR4_PRELIM
((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+#define C
ONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS
_OR_TIMING_SDRAM)
+#define C
ONFIG_SYS_BR4_PRELIM
((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
/*
* Memory Periodic Timer Prescaler
/*
* Memory Periodic Timer Prescaler
@@
-387,34
+400,34
@@
* 80 Mhz => 80.000.000 / Divider = 156
*/
* 80 Mhz => 80.000.000 / Divider = 156
*/
-#define C
FG_MAMR_PTA
234
+#define C
ONFIG_SYS_MAMR_PTA
234
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
- * #define C
FG_MPTPR_2BK_2K
MPTPR_PTP_DIV32 for 2 banks
- * #define C
FG_MPTPR_1BK_2K
MPTPR_PTP_DIV64 for 1 bank
+ * #define C
ONFIG_SYS_MPTPR_2BK_2K
MPTPR_PTP_DIV32 for 2 banks
+ * #define C
ONFIG_SYS_MPTPR_1BK_2K
MPTPR_PTP_DIV64 for 1 bank
*/
*/
-#define C
FG_MPTPR_2BK_4K
MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define C
FG_MPTPR_1BK_4K
MPTPR_PTP_DIV32 /* setting for 1 bank */
+#define C
ONFIG_SYS_MPTPR_2BK_4K
MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define C
ONFIG_SYS_MPTPR_1BK_4K
MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define C
FG_MPTPR_2BK_8K
MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define C
FG_MPTPR_1BK_8K
MPTPR_PTP_DIV16 /* setting for 1 bank */
+#define C
ONFIG_SYS_MPTPR_2BK_8K
MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define C
ONFIG_SYS_MPTPR_1BK_8K
MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
-#define C
FG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE
| \
+#define C
ONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE
| \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
-#define C
FG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE
| \
+#define C
ONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE
| \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
@@
-436,58
+449,58
@@
/****************************************************************/
/* NAND */
/****************************************************************/
/* NAND */
-#define CFG_NAND_BASE NAND_BASE
+#define CONFIG_NAND_LEGACY
+#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
-#define C
FG_MAX_NAND_DEVICE
1
+#define C
ONFIG_SYS_MAX_NAND_DEVICE
1
#undef NAND_NO_RB
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#undef NAND_NO_RB
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
#define NAND_DISABLE_CE(nand) \
do { \
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
#define NAND_DISABLE_CE(nand) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
- (((volatile immap_t *)C
FG
_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
+ (((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
} while(0)
#ifndef NAND_NO_RB
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
} while(0)
#ifndef NAND_NO_RB
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
- while ((((volatile immap_t *)C
FG
_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
+ while ((((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
if (++_tries > 100000) \
break; \
} while (0)
@@
-515,8
+528,8
@@
/*****************************************************************************/
/*****************************************************************************/
-#define C
FG
_DIRECT_FLASH_TFTP
-#define C
FG
_DIRECT_NAND_TFTP
+#define C
ONFIG_SYS
_DIRECT_FLASH_TFTP
+#define C
ONFIG_SYS
_DIRECT_NAND_TFTP
/*****************************************************************************/
/*****************************************************************************/
@@
-525,7
+538,7
@@
*/
#define STATUS_LED_BIT 0x00000080 /* bit 24 */
*/
#define STATUS_LED_BIT 0x00000080 /* bit 24 */
-#define STATUS_LED_PERIOD (C
FG
_HZ / 2)
+#define STATUS_LED_PERIOD (C
ONFIG_SYS
_HZ / 2)
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
@@
-540,15
+553,15
@@
typedef unsigned int led_id_t;
#define __led_toggle(_msk) \
do { \
#define __led_toggle(_msk) \
do { \
- ((volatile immap_t *)C
FG
_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+ ((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
} while(0)
#define __led_set(_msk, _st) \
do { \
if ((_st)) \
} while(0)
#define __led_set(_msk, _st) \
do { \
if ((_st)) \
- ((volatile immap_t *)C
FG
_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+ ((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
else \
else \
- ((volatile immap_t *)C
FG
_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+ ((volatile immap_t *)C
ONFIG_SYS
_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
} while(0)
#define __led_init(msk, st) __led_set(msk, st)
} while(0)
#define __led_init(msk, st) __led_set(msk, st)
@@
-557,16
+570,15
@@
typedef unsigned int led_id_t;
/******************************************************************************/
/******************************************************************************/
-#define C
FG_CONSOLE_IS_IN_ENV
1
-#define C
FG_CONSOLE_OVERWRITE_ROUTINE
1
-#define C
FG_CONSOLE_ENV_OVERWRITE
1
+#define C
ONFIG_SYS_CONSOLE_IS_IN_ENV
1
+#define C
ONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
1
+#define C
ONFIG_SYS_CONSOLE_ENV_OVERWRITE
1
/******************************************************************************/
/* use board specific hardware */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG
/******************************************************************************/
/* use board specific hardware */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
/*****************************************************************************/
/*****************************************************************************/
@@
-576,11
+588,8
@@
typedef unsigned int led_id_t;
/*****************************************************************************/
/*****************************************************************************/
-/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
+/* pass open firmware flattened device tree */
+#define CONFIG_OF_LIBFDT 1
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)