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Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
[platform/kernel/u-boot.git]
/
include
/
configs
/
stxgp3.h
diff --git
a/include/configs/stxgp3.h
b/include/configs/stxgp3.h
index
c2497ad
..
939a964
100644
(file)
--- a/
include/configs/stxgp3.h
+++ b/
include/configs/stxgp3.h
@@
-109,12
+109,9
@@
#ifdef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#ifdef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
-#else
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
#endif
-#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR 0xfdf00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_FSL_DDR1
/* DDR Setup */
#define CONFIG_FSL_DDR1
@@
-123,7
+120,7
@@
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_
DDR_DLL
/* possible DLL fix needed */
+#define CONFIG_
SYS_FSL_ERRATUM_DDR_MSYNC_IN
/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@
-176,7
+173,6
@@
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/*
#endif
/*
@@
-212,7
+208,6
@@
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
@@
-231,10
+226,6
@@
#if defined(CONFIG_TSEC_ENET)
#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
@@
-263,8
+254,8
@@
* - Select bus for bd/buffers
* - Full duplex
*/
* - Select bus for bd/buffers
* - Full duplex
*/
- #define CONFIG_SYS_CMXFCR_MASK
(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE
(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CONFIG_SYS_CMXFCR_MASK
2
(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CONFIG_SYS_CMXFCR_VALUE
2
(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
#if 0
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
#if 0
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
@@
-385,8
+376,8
@@
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_GP3
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_GP3
-#define CONFIG_ROOTPATH
/gppproot
-#define CONFIG_BOOTFILE
uImage
+#define CONFIG_ROOTPATH
"/gppproot"
+#define CONFIG_BOOTFILE
"uImage"
#define CONFIG_LOADADDR 0x1000000
#endif /* __CONFIG_H */
#define CONFIG_LOADADDR 0x1000000
#endif /* __CONFIG_H */