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Merge branch '2019-03-25-master-imports'
[platform/kernel/u-boot.git]
/
include
/
configs
/
socrates.h
diff --git
a/include/configs/socrates.h
b/include/configs/socrates.h
index
3491944
..
3f84fab
100644
(file)
--- a/
include/configs/socrates.h
+++ b/
include/configs/socrates.h
@@
-1,3
+1,4
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
@@
-6,8
+7,6
@@
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
*/
/*
@@
-22,11
+21,6
@@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
/*
* Only possible on E500 Version 2 or newer cores.
*/
@@
-66,7
+60,6
@@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@
-115,9
+108,6
@@
#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
-#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
-
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@
-174,7
+164,6
@@
/* Serial Port */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
@@
-225,7
+214,6
@@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC3 1