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Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI
[platform/kernel/u-boot.git]
/
include
/
configs
/
socfpga_common.h
diff --git
a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index
baa2143
..
31f95f5
100644
(file)
--- a/
include/configs/socfpga_common.h
+++ b/
include/configs/socfpga_common.h
@@
-5,6
+5,8
@@
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
+#include <linux/stringify.h>
+
/*
* High level configuration
*/
/*
* High level configuration
*/
@@
-16,19
+18,19
@@
* Memory configurations
*/
#define PHYS_SDRAM_1 0x0
* Memory configurations
*/
#define PHYS_SDRAM_1 0x0
-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
+#define CONFIG_SPL_PAD_TO 0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CONFIG_SPL_PAD_TO 0x40000
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
#endif
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
+ CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
#endif
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
#endif
@@
-94,21
+96,19
@@
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#ifndef CONFIG_SYS_TIMER_RATE
#define CONFIG_SYS_TIMER_RATE 25000000
#endif
#define CONFIG_SYS_TIMER_RATE 25000000
#endif
+#endif
/*
* L4 Watchdog
*/
/*
* L4 Watchdog
*/
-#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
-#endif
/*
* MMC Driver
/*
* MMC Driver
@@
-124,7
+124,6
@@
*/
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE 1
*/
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
@@
-146,7
+145,6
@@
unsigned int cm_get_qspi_controller_clk_hz(void);
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
@@
-157,21
+155,10
@@
unsigned int cm_get_qspi_controller_clk_hz(void);
/*
* U-Boot environment
*/
/*
* U-Boot environment
*/
-#if !defined(CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE (8 * 1024)
-#endif
/* Environment for SDMMC boot */
/* Environment for SDMMC boot */
-#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
-#endif
/* Environment for QSPI boot */
/* Environment for QSPI boot */
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET 0x00100000
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#endif
/*
* SPL
/*
* SPL
@@
-196,10
+183,9
@@
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
/* SPL SDMMC boot support */
#endif
/* SPL SDMMC boot support */
-#ifdef CONFIG_SPL_MMC
_SUPPORT
+#ifdef CONFIG_SPL_MMC
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
@@
-210,13
+196,6
@@
unsigned int cm_get_qspi_controller_clk_hz(void);
/* SPL QSPI boot support */
/* SPL NAND boot support */
/* SPL QSPI boot support */
/* SPL NAND boot support */
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
-#endif
-#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD