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SPDX: Convert all of our single license tags to Linux Kernel style
[platform/kernel/u-boot.git]
/
include
/
configs
/
sh7757lcr.h
diff --git
a/include/configs/sh7757lcr.h
b/include/configs/sh7757lcr.h
index
bee1a1d
..
95d70bc
100644
(file)
--- a/
include/configs/sh7757lcr.h
+++ b/
include/configs/sh7757lcr.h
@@
-1,9
+1,8
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the sh7757lcr board
*
* Copyright (C) 2011 Renesas Solutions Corp.
/*
* Configuation settings for the sh7757lcr board
*
* Copyright (C) 2011 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SH7757LCR_H
*/
#ifndef __SH7757LCR_H
@@
-12,8
+11,6
@@
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR_DDR_ECC 1
-#define CONFIG_SYS_TEXT_BASE 0x8ef80000
-
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
@@
-23,7
+20,6
@@
#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
@@
-33,7
+29,6
@@
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
224 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
224 * 1024 * 1024)
-#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
@@
-48,7
+43,6
@@
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* Ether */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* Ether */
-#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
@@
-66,11
+60,9
@@
#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
/* SPI */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
/* SPI */
-#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000