-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */