-#define CFG_GRER0_VAL 0x00000000
-#define CFG_GRER1_VAL 0x00000000
-#define CFG_GRER2_VAL 0x00000000
-#define CFG_GFER0_VAL 0x00000000
-#define CFG_GFER1_VAL 0x00000000
-#define CFG_GFER2_VAL 0x00000000
-
-#define CFG_GAFR0_L_VAL 0x00000000
-#define CFG_GAFR0_U_VAL 0x00000000
-#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
-#define CFG_GAFR1_U_VAL 0x00000000
-#define CFG_GAFR2_L_VAL 0x00000000
-#define CFG_GAFR2_U_VAL 0x00000000
-
-#define CFG_PSSR_VAL 0x20
-#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
-#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_GRER0_VAL 0x00000000
+#define CONFIG_SYS_GRER1_VAL 0x00000000
+#define CONFIG_SYS_GRER2_VAL 0x00000000
+#define CONFIG_SYS_GFER0_VAL 0x00000000
+#define CONFIG_SYS_GFER1_VAL 0x00000000
+#define CONFIG_SYS_GFER2_VAL 0x00000000
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
+#define CONFIG_SYS_GAFR0_U_VAL 0x00000000
+#define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
+#define CONFIG_SYS_GAFR1_U_VAL 0x00000000
+#define CONFIG_SYS_GAFR2_L_VAL 0x00000000
+#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+
+#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
+#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */