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common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
[platform/kernel/u-boot.git]
/
include
/
configs
/
omap3_zoom2.h
diff --git
a/include/configs/omap3_zoom2.h
b/include/configs/omap3_zoom2.h
index
701a296
..
2b07666
100644
(file)
--- a/
include/configs/omap3_zoom2.h
+++ b/
include/configs/omap3_zoom2.h
@@
-29,7
+29,6
@@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
/*
* High Level Configuration Options
/*
* High Level Configuration Options
@@
-64,9
+63,9
@@
/*
* Size of malloc() pool
*/
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE
SZ_128K /* Total Size Environment
*/
+#define CONFIG_ENV_SIZE
(128 << 10) /* 128 KiB
*/
/* Sector */
/* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE +
SZ_128K
)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE +
(128 << 10)
)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
@@
-99,6
+98,9
@@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
@@
-140,6
+142,7
@@
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
@@
-147,6
+150,12
@@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@
-158,8
+167,6
@@
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* Environment information */
#define CONFIG_BOOTDELAY 10
/* Environment information */
#define CONFIG_BOOTDELAY 10
@@
-194,10
+201,10
@@
*
* The stack sizes are set up in start.S using these settings
*/
*
* The stack sizes are set up in start.S using these settings
*/
-#define CONFIG_STACKSIZE
SZ_128K
+#define CONFIG_STACKSIZE
(128 << 10) /* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ
SZ_4K
-#define CONFIG_STACKSIZE_FIQ
SZ_4K
+#define CONFIG_STACKSIZE_IRQ
(4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ
(4 << 10) /* FIQ stack 4 KiB */
#endif
/*-----------------------------------------------------------------------
#endif
/*-----------------------------------------------------------------------
@@
-205,7
+212,7
@@
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE
SZ_32M /* at least 32 meg
*/
+#define PHYS_SDRAM_1_SIZE
(32 << 20) /* at least 32 MiB
*/
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
@@
-224,7
+231,7
@@
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN
SZ_256K
/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN
(256 << 10)
/* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_SYS_FLASH_BASE boot_flash_base
@@
-246,8
+253,7
@@
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__
-extern gpmc_csx_t *nand_cs_base;
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;