#else
/* No DDR init -> run in L2 cache with limited resources */
#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
#endif
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
#else
/* No DDR init -> run in L2 cache with limited resources */
#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
#endif
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000