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Merge git://git.denx.de/u-boot-socfpga
[platform/kernel/u-boot.git]
/
include
/
configs
/
mx7dsabresd.h
diff --git
a/include/configs/mx7dsabresd.h
b/include/configs/mx7dsabresd.h
index
8759685
..
39d29de
100644
(file)
--- a/
include/configs/mx7dsabresd.h
+++ b/
include/configs/mx7dsabresd.h
@@
-1,9
+1,8
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX7D SABRESD board.
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX7D SABRESD board.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX7D_SABRESD_CONFIG_H
*/
#ifndef __MX7D_SABRESD_CONFIG_H
@@
-11,7
+10,6
@@
#include "mx7_common.h"
#include "mx7_common.h"
-#define CONFIG_DBG_MONITOR
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
@@
-19,21
+17,12
@@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-/* Uncomment to enable secure boot support */
-/* #define CONFIG_SECURE_BOOT */
-#define CONFIG_CSF_SIZE 0x4000
-
/* Network */
#define CONFIG_FEC_MXC
/* Network */
#define CONFIG_FEC_MXC
-#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_PHYLIB
#define CONFIG_PHY_BROADCOM
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
#define CONFIG_PHY_BROADCOM
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
@@
-41,20
+30,12
@@
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
@@
-185,10
+166,7
@@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
@@
-200,19
+178,14
@@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
+/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
*/
#ifdef CONFIG_NAND_MXS
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
*/
#ifdef CONFIG_NAND_MXS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
@@
-220,12
+193,9
@@
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
-#define CONFIG_APBH_DMA
-#define CONFIG_APBH_DMA_BURST
-#define CONFIG_APBH_DMA_BURST8
#endif
#endif
-#define CONFIG_ENV_OFFSET (
8
* SZ_64K)
+#define CONFIG_ENV_OFFSET (
12
* SZ_64K)
#ifdef CONFIG_NAND_MXS
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
#ifdef CONFIG_NAND_MXS
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
@@
-237,43
+207,24
@@
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_IMX_THERMAL
#define CONFIG_USBD_HS
#define CONFIG_IMX_THERMAL
#define CONFIG_USBD_HS
-#define CONFIG_USB_FUNCTION_MASS_STORAGE
-
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#endif
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_BAR
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 40000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SYS_FSL_QSPI_AHB
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_64M
#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_64M
#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR