+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+
+#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
+#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1 0x04322000
+#define CFG_SDRAM0_MCOPT2 0x00000000
+#define CFG_SDRAM0_MODT0 0x01800000
+#define CFG_SDRAM0_MODT1 0x00000000
+#define CFG_SDRAM0_CODT 0x0080f837
+#define CFG_SDRAM0_RTR 0x06180000
+#define CFG_SDRAM0_INITPLR0 0xa8380000
+#define CFG_SDRAM0_INITPLR1 0x81900400
+#define CFG_SDRAM0_INITPLR2 0x81020000
+#define CFG_SDRAM0_INITPLR3 0x81030000
+#define CFG_SDRAM0_INITPLR4 0x81010404
+#define CFG_SDRAM0_INITPLR5 0x81000542
+#define CFG_SDRAM0_INITPLR6 0x81900400
+#define CFG_SDRAM0_INITPLR7 0x8D080000
+#define CFG_SDRAM0_INITPLR8 0x8D080000
+#define CFG_SDRAM0_INITPLR9 0x8D080000
+#define CFG_SDRAM0_INITPLR10 0x8D080000
+#define CFG_SDRAM0_INITPLR11 0x81000442
+#define CFG_SDRAM0_INITPLR12 0x81010780
+#define CFG_SDRAM0_INITPLR13 0x81010400
+#define CFG_SDRAM0_INITPLR14 0x00000000
+#define CFG_SDRAM0_INITPLR15 0x00000000
+#define CFG_SDRAM0_RQDC 0x80000038
+#define CFG_SDRAM0_RFDC 0x00000209
+#define CFG_SDRAM0_RDCC 0x40000000
+#define CFG_SDRAM0_DLCR 0x030000a5
+#define CFG_SDRAM0_CLKTR 0x80000000
+#define CFG_SDRAM0_WRDTR 0x00000000
+#define CFG_SDRAM0_SDTR1 0x80201000
+#define CFG_SDRAM0_SDTR2 0x32204232
+#define CFG_SDRAM0_SDTR3 0x080b0d1a
+#define CFG_SDRAM0_MMODE 0x00000442
+#define CFG_SDRAM0_MEMODE 0x00000404