+ CFG_POST_UART | \
+ CFG_POST_SYSMON | \
+ CFG_POST_WATCHDOG | \
+ CFG_POST_DSP | \
+ CFG_POST_BSPEC1 | \
+ CFG_POST_BSPEC2 | \
+ CFG_POST_BSPEC3 | \
+ CFG_POST_BSPEC4 | \
+ CFG_POST_BSPEC5)
+
+#define CONFIG_POST_WATCHDOG {\
+ "Watchdog timer test", \
+ "watchdog", \
+ "This test checks the watchdog timer.", \
+ POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
+ &lwmon5_watchdog_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_WATCHDOG \
+ }
+
+#define CONFIG_POST_BSPEC1 {\
+ "dsPIC init test", \
+ "dspic_init", \
+ "This test returns result of dsPIC READY test run earlier.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_init_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC1 \
+ }
+
+#define CONFIG_POST_BSPEC2 {\
+ "dsPIC test", \
+ "dspic", \
+ "This test gets result of dsPIC POST and dsPIC version.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC2 \
+ }
+
+#define CONFIG_POST_BSPEC3 {\
+ "FPGA test", \
+ "fpga", \
+ "This test checks FPGA registers and memory.", \
+ POST_RAM | POST_ALWAYS, \
+ &fpga_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC3 \
+ }
+
+#define CONFIG_POST_BSPEC4 {\
+ "GDC test", \
+ "gdc", \
+ "This test checks GDC registers and memory.", \
+ POST_RAM | POST_ALWAYS, \
+ &gdc_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC4 \
+ }
+
+#define CONFIG_POST_BSPEC5 {\
+ "SYSMON1 test", \
+ "sysmon1", \
+ "This test checks GPIO_62_EPX pin indicating power failure.", \
+ POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
+ &sysmon1_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC5 \
+ }
+
+#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */