-#define CONFIG_SYS_CLK_FREQ 125000000
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-#else
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-#endif
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
-/* CSU */
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M)
-
-/* PFE */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL