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MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
[platform/kernel/u-boot.git]
/
include
/
configs
/
kontron_sl28.h
diff --git
a/include/configs/kontron_sl28.h
b/include/configs/kontron_sl28.h
index
25cb8f6
..
df46e58
100644
(file)
--- a/
include/configs/kontron_sl28.h
+++ b/
include/configs/kontron_sl28.h
@@
-1,7
+1,7
@@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __SL28_H
-#define __SL28_H
+#ifndef __SL28_
CONFIG_
H
+#define __SL28_
CONFIG_
H
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
@@
-23,10
+23,8
@@
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/* early stack pointer */
/* early stack pointer */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
/* SMP */
#define CPU_RELEASE_ADDR secondary_boot_addr
/* SMP */
#define CPU_RELEASE_ADDR secondary_boot_addr
@@
-39,15
+37,8
@@
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-
/* SPL */
/* SPL */
-#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
/* GUID for capsule updatable firmware image */
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
/* GUID for capsule updatable firmware image */
@@
-86,4
+77,4
@@
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
-#endif /* __SL28_H */
+#endif /* __SL28_
CONFIG_
H */