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Makefile: move all Power Architecture boards into boards.cfg
[platform/kernel/u-boot.git]
/
include
/
configs
/
kmeter1.h
diff --git
a/include/configs/kmeter1.h
b/include/configs/kmeter1.h
index
869fd4c
..
9117842
100644
(file)
--- a/
include/configs/kmeter1.h
+++ b/
include/configs/kmeter1.h
@@
-30,9
+30,18
@@
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
+#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
+
+#define MTDIDS_DEFAULT "nor0=boot"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
@@
-72,6
+81,14
@@
#define CONFIG_SYS_IMMR 0xE0000000
/*
#define CONFIG_SYS_IMMR 0xE0000000
/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
+
+/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
@@
-142,9
+159,8
@@
/*
* The reserved memory
*/
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_
TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
#define CONFIG_SYS_PIGGY_SIZE 128
#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
#define CONFIG_SYS_PIGGY_SIZE 128
#define CONFIG_SYS_PAXE_BASE 0xA0000000
@@
-170,7
+186,9
@@
/*
* Local Bus Configuration & Clock Setup
*/
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
/*
* Init Local Bus Memory Controller:
/*
* Init Local Bus Memory Controller:
@@
-203,9
+221,9
@@
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
-#define CONFIG_SYS_MAX_FLASH_BANKS
2
/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS
1
/* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_BASE_1
}
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#undef CONFIG_SYS_FLASH_CHECKSUM
#undef CONFIG_SYS_FLASH_CHECKSUM
@@
-241,7
+259,6
@@
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@
-268,7
+285,7
@@
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "
FSL
UEC0"
+#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
@@
-279,7
+296,8
@@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif
/*
#endif
/*
@@
-324,6
+342,12
@@
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
+#endif
+
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
@@
-335,16
+359,17
@@
/*
* For booting Linux, the board info and command line data
/*
* For booting Linux, the board info and command line data
- * have to be in the first
8
MB of memory, since this is
+ * have to be in the first
256
MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (
8
<< 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (
256
<< 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_HID2 HID2_HBE
/*
@@
-429,11
+454,6
@@
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-#define MTDIDS_DEFAULT "nor2=app"
-#define MTDPARTS_DEFAULT \
- "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
- "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
-
/*
* Environment Configuration
*/
/*
* Environment Configuration
*/