-#define CM_BASE 0x10000000
-
-/* CM registers common to all integrator/CP CMs */
-#define OS_CTRL 0x0000000C
-#define CMMASK_REMAP 0x00000005 /* set remap & led */
-#define CMMASK_RESET 0x00000008
-#define OS_LOCK 0x00000014
-#define CMVAL_LOCK 0x0000A000 /* locking value */
-#define CMMASK_LOCK 0x0000005F /* locking value */
-#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
-#define OS_SDRAM 0x00000020
-#define OS_INIT 0x00000024
-#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
-#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
-#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
- * - PLL test clock bypassed
- * - bus clock ratio 2
- * - little endian
- * - vectors at zero
- */
-#endif /* CM1022xx */
-
-#define CMMASK_LE 0x00000008 /* little endian */
-#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
- * - divisor/ratio b00000001
- * bx
- * - HCLKDIV b000
- * bxx
- * - PLL BYPASS b00
- */
-
-/* Determine CM characteristics */
-
-#undef CONFIG_CM_MULTIPLE_SSRAM
-#undef CONFIG_CM_SPD_DETECT
-#undef CONFIG_CM_REMAP
-#undef CONFIG_CM_INIT
-#undef CONFIG_CM_TCRAM
-
-#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
-#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
-#endif